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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71df0d65278sm7881094b3a.160.2024.10.09.08.09.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 08:09:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728486556; x=1729091356; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=cc9On083uJcJ4nXjMqsVER0drsrso2XobYAn0o66lak=; b=CxbG1yFBRQtI2UjNkdokLSUfWvUAxpOk3KZzS/Ot3BTbV04GdQgKO7PPn+Gua9BwPv 0zoWp3F3C4ULVNrmQvn1LYXzmxhFaAgB/mVSnczMCNHRBubmRMhuhjS/dx6qZBwUAhkY nj9VBpVApyPk1YYlFllHCv2+uyUMKWpO3erh0Xz17zjey+yaaDNXenl5MR0Vp0RCnntx b+l/ZaUtcBqgIhFfpzbwfFCUyN1li+5I/Z1MU28WWBc86Aapow7RP099YmGrNa5ZC5WS RyQrxorTEvhjG6bX6mVKlpFnAfMbZVwj9oFbsO5Escr2dZFxg3N81OgBP85ZRrwi8E4z tMIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728486556; x=1729091356; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cc9On083uJcJ4nXjMqsVER0drsrso2XobYAn0o66lak=; b=sMfNi8mT4fFbyFRconv2zoJsL2iY9Ev+92PGf3xzNmNJAmUwFi1YrIeAOa+1COeCgW QxjUzDvL5WvfMVZFV6DuoaTeqok+JiP9KXjXq3uSXBbQTopFfDFh727XE5/A97gZU2N9 R0yCUxwioRiWTaVjlFZf17OAXCvtkrmDMyiPYJ7uX06aTGOl6JAM3UKy/LPIp78XEtum uIsMewoRmuXIjRRMhTSpEzmhjlM+CHYm+oXAH9v8Frue7/6esfjvVEYPn6znDDlpJ9iP dfpRRJP6Wk7SS6eDBA+y4lkgutrt+83j+SJolMOR3yxZkWR467y2kuj+Iwxe03D1p9z0 YOhg== X-Gm-Message-State: AOJu0YwiYMbm6uOXAYr2+7bSCSy1D09guEDbUBQ9X6Rf4uR2mh7Z76BV llE2Qq6pVWrKdWIHmjaWjdJnImcGEczSyfRwzStaoAnSki9WXdxdFPx4vhLYzOTngcaiKcruQ90 B X-Google-Smtp-Source: AGHT+IHlws/m7vB9sx1QyRNFWR8LrP4HM0bf9L3WA5lSr4eae3wHeH/tVgx+IzxjyrfTuVucb85DTg== X-Received: by 2002:a05:6a21:9102:b0:1d6:d5c1:e504 with SMTP id adf61e73a8af0-1d8a3c1e587mr5562929637.26.1728486556599; Wed, 09 Oct 2024 08:09:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [NOTYET PATCH 22/23] accel/tcg: Drop TCGCPUOps.tlb_fill Date: Wed, 9 Oct 2024 08:08:54 -0700 Message-ID: <20241009150855.804605-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009150855.804605-1-richard.henderson@linaro.org> References: <20241009150855.804605-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1728486757935116600 Content-Type: text/plain; charset="utf-8" Now that all targets have been converted to tlb_fill_align, remove the tlb_fill hook. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/hw/core/tcg-cpu-ops.h | 10 ---------- accel/tcg/cputlb.c | 19 ++++--------------- 2 files changed, 4 insertions(+), 25 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index c932690621..e73c8a03de 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -157,16 +157,6 @@ struct TCGCPUOps { bool (*tlb_fill_align)(CPUState *cpu, CPUTLBEntryFull *out, vaddr addr, MMUAccessType access_type, int mmu_idx, MemOp memop, int size, bool probe, uintptr_t ra= ); - /** - * @tlb_fill: Handle a softmmu tlb miss - * - * If the access is valid, call tlb_set_page and return true; - * if the access is invalid and probe is true, return false; - * otherwise raise an exception and do not return. - */ - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); /** * @do_transaction_failed: Callback for handling failed memory transac= tions * (ie bus faults or external aborts; not MMU faults) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 47b9557bb8..55c7bf737b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1251,23 +1251,12 @@ static bool tlb_fill_align(CPUState *cpu, vaddr add= r, MMUAccessType type, int mmu_idx, MemOp memop, int size, bool probe, uintptr_t ra) { - const TCGCPUOps *ops =3D cpu->cc->tcg_ops; CPUTLBEntryFull full; =20 - if (ops->tlb_fill_align) { - if (ops->tlb_fill_align(cpu, &full, addr, type, mmu_idx, - memop, size, probe, ra)) { - tlb_set_page_full(cpu, mmu_idx, addr, &full); - return true; - } - } else { - /* Legacy behaviour is alignment before paging. */ - if (addr & ((1u << memop_alignment_bits(memop)) - 1)) { - ops->do_unaligned_access(cpu, addr, type, mmu_idx, ra); - } - if (ops->tlb_fill(cpu, addr, size, type, mmu_idx, probe, ra)) { - return true; - } + if (cpu->cc->tcg_ops->tlb_fill_align(cpu, &full, addr, type, mmu_idx, + memop, size, probe, ra)) { + tlb_set_page_full(cpu, mmu_idx, addr, &full); + return true; } assert(probe); return false; --=20 2.43.0