From nobody Sat Nov 23 23:15:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1728444359; cv=none; d=zohomail.com; s=zohoarc; b=i2CfrjfEHk3BqoicS7t+6y3f6ZWCTYDujGU7BuW8LWZ4GqQ0SArqyQkkz/dOL4l6n7EY2U6S/CELzQegyL7ZmDrYf2OLZ9QYLUieyUPDZgIwS4JWClG1+bXuz9CP5gxze0rqe06ikxuOmpDdv/QeIauragC36q6NiGP33JgL+x8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1728444359; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=OJVyI6CaHk/YKbi9IYIuXKhhsHaX3OnN6Su41+B66SI=; b=G+KNuO/Xi4uEnFt8+JYC0DiKG2jA0eQfiFQEki/ri6nnTVg5KTsX0TjTF4yBgAYUStHgzBz23TjpAoqCPfKEgUE8fbP0FciEHOUcl2rWiUk06iBGH+By3NGTsIlIXKGMLIaLjGiAc2pJKtD/M9EVkYIA6GNDidPCT3wY/KG9SKw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1728444359482884.9657528343577; Tue, 8 Oct 2024 20:25:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1syNKT-0006E9-1f; Tue, 08 Oct 2024 23:25:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1syNKQ-0006A9-P0; Tue, 08 Oct 2024 23:25:34 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1syNKO-0004wq-75; Tue, 08 Oct 2024 23:25:34 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4XNdT343p3z6LDBw; Wed, 9 Oct 2024 11:21:11 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id 4734C140114; Wed, 9 Oct 2024 11:25:30 +0800 (CST) Received: from 00293818-MRGF.huawei.com (10.126.173.89) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Wed, 9 Oct 2024 05:25:11 +0200 To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFC V4 18/33] hw/acpi: Simulate *persistent* vCPU presence to Guest in ACPI _STA.{PRES, ENA} Bits Date: Wed, 9 Oct 2024 04:18:00 +0100 Message-ID: <20241009031815.250096-19-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009031815.250096-1-salil.mehta@huawei.com> References: <20241009031815.250096-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.173.89] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500007.china.huawei.com (7.182.85.172) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1728444360926116600 Certain CPU architecture specifications [1][2][3] prohibit changes to the C= PUs *presence* after the kernel has booted. This is because many system initializations depend on the exact CPU count at boot time and do not expec= t it to change afterward. For example, components like interrupt controllers tha= t are closely coupled with CPUs, or various per-CPU features, may not support configuration changes once the kernel has been initialized. This requirement poses a challenge for virtualization features like vCPU hotplug. To address this, changes to the ACPI AML are necessary to update t= he `_STA.PRES` (presence) and `_STA.ENA` (enabled) bits accordingly during gue= st initialization, as well as when vCPUs are hot-plugged or hot-unplugged. The presence of unplugged vCPUs may need to be deliberately *simulated* at the = ACPI level to maintain a *persistent* view of vCPUs for the guest kernel. Introduce an `acpi_persistent` property, which can be used to initialize the ACPI vCPU `presence` state accordingly. Architectures that require ACPI to expose a persistent view of vCPUs can override its default value. Refer to = the subsequent patches for its usage. References: [1] KVMForum 2023 Presentation: Challenges Revisited in Supporting Virt CPU= Hotplug on architectures that don=E2=80=99t Support CPU Hotplug (like ARM64) a. Kernel Link: https://kvm-forum.qemu.org/2023/KVM-forum-cpu-hotplug_7= OJ1YyJ.pdf b. Qemu Link: https://kvm-forum.qemu.org/2023/Challenges_Revisited_in_= Supporting_Virt_CPU_Hotplug_-__ii0iNb3.pdf [2] KVMForum 2020 Presentation: Challenges in Supporting Virtual CPU Hotplu= g on SoC Based Systems (like ARM64) Link: https://kvmforum2020.sched.com/event/eE4m [3] Check comment 5 in the bugzilla entry Link: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4481#c5 Signed-off-by: Salil Mehta --- cpu-target.c | 1 + hw/acpi/cpu.c | 70 +++++++++++++++++++++++++++++++--- hw/acpi/generic_event_device.c | 11 ++++++ include/hw/acpi/cpu.h | 23 +++++++++++ include/hw/core/cpu.h | 10 +++++ 5 files changed, 110 insertions(+), 5 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index 499facf774..c8a29ab495 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -200,6 +200,7 @@ static Property cpu_common_props[] =3D { */ DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_BOOL("acpi-persistent", CPUState, acpi_persistent, false), #endif DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index 2d6afcfff7..d5d0363d08 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -63,10 +63,11 @@ static uint64_t cpu_hotplug_rd(void *opaque, hwaddr add= r, unsigned size) cdev =3D &cpu_st->devs[cpu_st->selector]; switch (addr) { case ACPI_CPU_FLAGS_OFFSET_RW: /* pack and return is_* fields */ - val |=3D cdev->cpu ? 1 : 0; + val |=3D cdev->is_enabled ? 1 : 0; val |=3D cdev->is_inserting ? 2 : 0; val |=3D cdev->is_removing ? 4 : 0; val |=3D cdev->fw_remove ? 16 : 0; + val |=3D cdev->is_present ? 32 : 0; trace_cpuhp_acpi_read_flags(cpu_st->selector, val); break; case ACPI_CPU_CMD_DATA_OFFSET_RW: @@ -225,7 +226,40 @@ void cpu_hotplug_hw_init(MemoryRegion *as, Object *own= er, state->dev_count =3D id_list->len; state->devs =3D g_new0(typeof(*state->devs), state->dev_count); for (i =3D 0; i < id_list->len; i++) { - state->devs[i].cpu =3D CPU(id_list->cpus[i].cpu); + struct CPUState *cpu =3D CPU(id_list->cpus[i].cpu); + /* + * In most architectures, CPUs that are marked as ACPI 'present' a= re + * also ACPI 'enabled' by default. These states remain consistent = at + * both the QOM and ACPI levels. + */ + if (qemu_enabled_cpu(cpu)) { + state->devs[i].is_enabled =3D true; + state->devs[i].is_present =3D true; + state->devs[i].cpu =3D cpu; + } else { + state->devs[i].is_enabled =3D false; + /* + * In some architectures, even 'unplugged' or 'disabled' QOM C= PUs + * may be exposed as ACPI 'present.' This approach provides a + * persistent view of the vCPUs to the guest kernel. This coul= d be + * due to an architectural constraint that requires every per-= CPU + * component to be present at boot time, meaning the exact cou= nt of + * vCPUs must be known and cannot be altered after the kernel = has + * booted. As a result, the vCPU states at the QOM and ACPI le= vels + * might become inconsistent. However, in such cases, the pres= ence + * of vCPUs has been deliberately simulated at the ACPI level. + */ + if (acpi_persistent_cpu(cpu)) { + state->devs[i].is_present =3D true; + /* + * `CPUHotplugState::AcpiCpuStatus::cpu` becomes insignifi= cant + * in this case + */ + } else { + state->devs[i].is_present =3D qemu_present_cpu(cpu); + state->devs[i].cpu =3D cpu; + } + } state->devs[i].arch_id =3D id_list->cpus[i].arch_id; } memory_region_init_io(&state->ctrl_reg, owner, &cpu_hotplug_ops, state, @@ -258,6 +292,8 @@ void acpi_cpu_plug_cb(HotplugHandler *hotplug_dev, } =20 cdev->cpu =3D CPU(dev); + cdev->is_present =3D true; + cdev->is_enabled =3D true; if (dev->hotplugged) { cdev->is_inserting =3D true; acpi_send_event(DEVICE(hotplug_dev), ACPI_CPU_HOTPLUG_STATUS); @@ -289,6 +325,11 @@ void acpi_cpu_unplug_cb(CPUHotplugState *cpu_st, return; } =20 + cdev->is_enabled =3D false; + if (!acpi_persistent_cpu(CPU(dev))) { + cdev->is_present =3D false; + } + cdev->cpu =3D NULL; } =20 @@ -299,6 +340,8 @@ static const VMStateDescription vmstate_cpuhp_sts =3D { .fields =3D (const VMStateField[]) { VMSTATE_BOOL(is_inserting, AcpiCpuStatus), VMSTATE_BOOL(is_removing, AcpiCpuStatus), + VMSTATE_BOOL(is_present, AcpiCpuStatus), + VMSTATE_BOOL(is_enabled, AcpiCpuStatus), VMSTATE_UINT32(ost_event, AcpiCpuStatus), VMSTATE_UINT32(ost_status, AcpiCpuStatus), VMSTATE_END_OF_LIST() @@ -336,6 +379,7 @@ const VMStateDescription vmstate_cpu_hotplug =3D { #define CPU_REMOVE_EVENT "CRMV" #define CPU_EJECT_EVENT "CEJ0" #define CPU_FW_EJECT_EVENT "CEJF" +#define CPU_PRESENT "CPRS" =20 void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures = opts, build_madt_cpu_fn build_madt_cpu, hwaddr base_addr, @@ -396,7 +440,9 @@ void build_cpus_aml(Aml *table, MachineState *machine, = CPUHotplugFeatures opts, aml_append(field, aml_named_field(CPU_EJECT_EVENT, 1)); /* tell firmware to do device eject, write only */ aml_append(field, aml_named_field(CPU_FW_EJECT_EVENT, 1)); - aml_append(field, aml_reserved_field(3)); + /* 1 if present, read only */ + aml_append(field, aml_named_field(CPU_PRESENT, 1)); + aml_append(field, aml_reserved_field(2)); aml_append(field, aml_named_field(CPU_COMMAND, 8)); aml_append(cpu_ctrl_dev, field); =20 @@ -426,6 +472,7 @@ void build_cpus_aml(Aml *table, MachineState *machine, = CPUHotplugFeatures opts, Aml *ctrl_lock =3D aml_name("%s.%s", cphp_res_path, CPU_LOCK); Aml *cpu_selector =3D aml_name("%s.%s", cphp_res_path, CPU_SELECTO= R); Aml *is_enabled =3D aml_name("%s.%s", cphp_res_path, CPU_ENABLED); + Aml *is_present =3D aml_name("%s.%s", cphp_res_path, CPU_PRESENT); Aml *cpu_cmd =3D aml_name("%s.%s", cphp_res_path, CPU_COMMAND); Aml *cpu_data =3D aml_name("%s.%s", cphp_res_path, CPU_DATA); Aml *ins_evt =3D aml_name("%s.%s", cphp_res_path, CPU_INSERT_EVENT= ); @@ -454,13 +501,26 @@ void build_cpus_aml(Aml *table, MachineState *machine= , CPUHotplugFeatures opts, { Aml *idx =3D aml_arg(0); Aml *sta =3D aml_local(0); + Aml *ifctx2; + Aml *else_ctx; =20 aml_append(method, aml_acquire(ctrl_lock, 0xFFFF)); aml_append(method, aml_store(idx, cpu_selector)); aml_append(method, aml_store(zero, sta)); - ifctx =3D aml_if(aml_equal(is_enabled, one)); + ifctx =3D aml_if(aml_equal(is_present, one)); { - aml_append(ifctx, aml_store(aml_int(0xF), sta)); + ifctx2 =3D aml_if(aml_equal(is_enabled, one)); + { + /* cpu is present and enabled */ + aml_append(ifctx2, aml_store(aml_int(0xF), sta)); + } + aml_append(ifctx, ifctx2); + else_ctx =3D aml_else(); + { + /* cpu is present but disabled */ + aml_append(else_ctx, aml_store(aml_int(0xD), sta)); + } + aml_append(ifctx, else_ctx); } aml_append(method, ifctx); aml_append(method, aml_release(ctrl_lock)); diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index 15b4c3ebbf..a4d78a534c 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -331,6 +331,16 @@ static const VMStateDescription vmstate_memhp_state = =3D { } }; =20 +static const VMStateDescription vmstate_cpuhp_state =3D { + .name =3D "acpi-ged/cpuhp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_CPU_HOTPLUG(cpuhp_state, AcpiGedState), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_ged_state =3D { .name =3D "acpi-ged-state", .version_id =3D 1, @@ -379,6 +389,7 @@ static const VMStateDescription vmstate_acpi_ged =3D { }, .subsections =3D (const VMStateDescription * const []) { &vmstate_memhp_state, + &vmstate_cpuhp_state, &vmstate_ghes_state, NULL } diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index 4d6ae5453f..1e2147a8ac 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -26,6 +26,8 @@ typedef struct AcpiCpuStatus { uint64_t arch_id; bool is_inserting; bool is_removing; + bool is_present; + bool is_enabled; bool fw_remove; uint32_t ost_event; uint32_t ost_status; @@ -93,4 +95,25 @@ static inline uint64_t acpi_get_cpu_archid(int cpu_index) =20 return possible_cpus->cpus[cpu_index].arch_id; } + +/** + * acpi_persistent_cpu: + * @cpu: The vCPU to check + * + * Checks if the vCPU state should always be reflected as *present* via AC= PI + * to the Guest. By default, this is False on all architectures and has to= be + * explicity set during initialization. + * + * Returns: True if it is ACPI 'persistent' CPU + * + */ +static inline bool acpi_persistent_cpu(CPUState *cpu) +{ + assert(cpu); + /* + * returns if 'Presence' of the vCPU is persistent and should be simul= ated + * via ACPI even after vCPUs have been unplugged in QOM + */ + return cpu->acpi_persistent; +} #endif diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fa6f1dbec9..2e62d5f1a5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -552,6 +552,16 @@ struct CPUState { * By default, `CPUState` objects are enabled across all architectures. */ bool disabled; + /* + * On certain architectures, to provide the guest kernel with a persis= tent + * view of vCPU presence, even when the QOM might not have a correspon= ding + * vCPU object, ACPI may need to simulate the presence of vCPUs while + * keeping them ACPI-disabled for the guest. This is achieved by retur= ning + * `_STA.PRES=3DTrue` and `_STA.Ena=3DFalse` for unplugged vCPUs in QE= MU's QOM. + * By default, this flag is set to FALSE and must be explicitly set to= TRUE + * on architectures like ARM. + */ + bool acpi_persistent; =20 /* TODO Move common fields from CPUArchState here. */ int cpu_index; --=20 2.34.1