From nobody Sat Nov 23 23:45:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1728444174; cv=none; d=zohomail.com; s=zohoarc; b=mRfcDjvgdJ5bq59LeYpIHpWHLExSukgX5Ffipu3lb8j4RsQJcWt7bwZjsSnnqhYscfW4F7AIg0Jk0X2WLf3tYogfzaQFG17+Pc9nEz2xlLjV18luqWgpZf4TevE7whnc61OZDd4ADMh/RmXU+dVGL3p8W+Dn8mnepTwNZSOs16M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1728444174; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Ir3xtn1cwIjlVMN6blVzQoVNliU7Or14JpWFRBXFOkc=; b=Am0kw+GRooPjvklyCPu6ynxFsF0EbujqiozPn/E4YjcRv89T0heO89MKNBQh3pSKoMP1zWHJ6b7jDs4uURbbgXMKANEeqC7fgYt3KStkTmbxb2ymiNS/P50TliTkaos6rDr+rW/LrHs78fYAHp+597RUoDtom12fu7Xq6PR+tuY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1728444174652446.54608812489005; Tue, 8 Oct 2024 20:22:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1syNHc-0000Gj-GA; Tue, 08 Oct 2024 23:22:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1syNHb-0000FE-0O; Tue, 08 Oct 2024 23:22:39 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1syNHY-0004aT-Bu; Tue, 08 Oct 2024 23:22:38 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4XNdPg5j8jz6L774; Wed, 9 Oct 2024 11:18:15 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id 7EDD2140452; Wed, 9 Oct 2024 11:22:34 +0800 (CST) Received: from 00293818-MRGF.huawei.com (10.126.173.89) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Wed, 9 Oct 2024 05:22:15 +0200 To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFC V4 09/33] hw/intc/arm-gicv3*: Changes required to (re)init the GICv3 vCPU Interface Date: Wed, 9 Oct 2024 04:17:51 +0100 Message-ID: <20241009031815.250096-10-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009031815.250096-1-salil.mehta@huawei.com> References: <20241009031815.250096-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.173.89] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500007.china.huawei.com (7.182.85.172) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1728444176115116600 Content-Type: text/plain; charset="utf-8" The GICv3 CPU interface must be (re)initialized when a vCPU is either cold-= or hot-plugged. System registers need to be defined and registered with the associated vCPU. For cold-plugged vCPUs, this occurs during the GICv3 realization phase, while for hot-plugged vCPUs, it happens during the GICv3 update notification. The latter will be addressed in subsequent patches. This process must be implemented for both emulation/TCG and KVM cases. This change adds the necessary support and refactors the existing code to maximi= ze reuse for both cold and hotplug vCPU initialization. Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta --- hw/intc/arm_gicv3.c | 1 + hw/intc/arm_gicv3_cpuif.c | 245 ++++++++++++++--------------- hw/intc/arm_gicv3_cpuif_common.c | 13 ++ hw/intc/arm_gicv3_kvm.c | 14 +- hw/intc/gicv3_internal.h | 1 + include/hw/intc/arm_gicv3_common.h | 1 + 6 files changed, 143 insertions(+), 132 deletions(-) diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 58e18fff54..2a30625916 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -459,6 +459,7 @@ static void arm_gicv3_class_init(ObjectClass *klass, vo= id *data) ARMGICv3Class *agc =3D ARM_GICV3_CLASS(klass); =20 agcc->post_load =3D arm_gicv3_post_load; + agcc->init_cpu_reginfo =3D gicv3_init_cpu_reginfo; device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_real= ize); } =20 diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 151f957d42..453d1296ea 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -3033,143 +3033,138 @@ static void gicv3_cpuif_el_change_hook(ARMCPU *cp= u, void *opaque) gicv3_cpuif_virt_irq_fiq_update(cs); } =20 -void gicv3_init_cpuif(GICv3State *s) +void gicv3_init_cpu_reginfo(CPUState *cs) { - /* Called from the GICv3 realize function; register our system - * registers with the CPU - */ - int i; + ARMCPU *cpu =3D ARM_CPU(cs); + GICv3CPUState *gcs =3D icc_cs_from_env(&cpu->env); =20 - for (i =3D 0; i < s->num_cpu; i++) { - ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i)); - GICv3CPUState *cs =3D &s->cpu[i]; + /* + * If the CPU doesn't define a GICv3 configuration, probably because + * in real hardware it doesn't have one, then we use default values + * matching the one used by most Arm CPUs. This applies to: + * cpu->gic_num_lrs + * cpu->gic_vpribits + * cpu->gic_vprebits + * cpu->gic_pribits + */ =20 - /* - * If the CPU doesn't define a GICv3 configuration, probably becau= se - * in real hardware it doesn't have one, then we use default values - * matching the one used by most Arm CPUs. This applies to: - * cpu->gic_num_lrs - * cpu->gic_vpribits - * cpu->gic_vprebits - * cpu->gic_pribits - */ + /* + * Note that we can't just use the GICv3CPUState as an opaque pointer + * in define_arm_cp_regs_with_opaque(), because when we're called back + * it might be with code translated by CPU 0 but run by CPU 1, in + * which case we'd get the wrong value. + * So instead we define the regs with no ri->opaque info, and + * get back to the GICv3CPUState from the CPUARMState. + * + * These CP regs callbacks can be called from either TCG or HVF code. + */ + define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); =20 - /* Note that we can't just use the GICv3CPUState as an opaque poin= ter - * in define_arm_cp_regs_with_opaque(), because when we're called = back - * it might be with code translated by CPU 0 but run by CPU 1, in - * which case we'd get the wrong value. - * So instead we define the regs with no ri->opaque info, and - * get back to the GICv3CPUState from the CPUARMState. - * - * These CP regs callbacks can be called from either TCG or HVF co= de. - */ - define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); + /* + * If the CPU implements FEAT_NMI and FEAT_GICv3 it must also + * implement FEAT_GICv3_NMI, which is the CPU interface part + * of NMI support. This is distinct from whether the GIC proper + * (redistributors and distributor) have NMI support. In QEMU + * that is a property of the GIC device in s->nmi_support; + * cs->nmi_support indicates the CPU interface's support. + */ + if (cpu_isar_feature(aa64_nmi, cpu)) { + gcs->nmi_support =3D true; + define_arm_cp_regs(cpu, gicv3_cpuif_gicv3_nmi_reginfo); + } =20 - /* - * If the CPU implements FEAT_NMI and FEAT_GICv3 it must also - * implement FEAT_GICv3_NMI, which is the CPU interface part - * of NMI support. This is distinct from whether the GIC proper - * (redistributors and distributor) have NMI support. In QEMU - * that is a property of the GIC device in s->nmi_support; - * cs->nmi_support indicates the CPU interface's support. - */ - if (cpu_isar_feature(aa64_nmi, cpu)) { - cs->nmi_support =3D true; - define_arm_cp_regs(cpu, gicv3_cpuif_gicv3_nmi_reginfo); - } + /* + * The CPU implementation specifies the number of supported + * bits of physical priority. For backwards compatibility + * of migration, we have a compat property that forces use + * of 8 priority bits regardless of what the CPU really has. + */ + if (gcs->gic->force_8bit_prio) { + gcs->pribits =3D 8; + } else { + gcs->pribits =3D cpu->gic_pribits ?: 5; + } =20 - /* - * The CPU implementation specifies the number of supported - * bits of physical priority. For backwards compatibility - * of migration, we have a compat property that forces use - * of 8 priority bits regardless of what the CPU really has. - */ - if (s->force_8bit_prio) { - cs->pribits =3D 8; - } else { - cs->pribits =3D cpu->gic_pribits ?: 5; - } + /* + * The GICv3 has separate ID register fields for virtual priority + * and preemption bit values, but only a single ID register field + * for the physical priority bits. The preemption bit count is + * always the same as the priority bit count, except that 8 bits + * of priority means 7 preemption bits. We precalculate the + * preemption bits because it simplifies the code and makes the + * parallels between the virtual and physical bits of the GIC + * a bit clearer. + */ + gcs->prebits =3D gcs->pribits; + if (gcs->prebits =3D=3D 8) { + gcs->prebits--; + } + /* + * Check that CPU code defining pribits didn't violate + * architectural constraints our implementation relies on. + */ + g_assert(gcs->pribits >=3D 4 && gcs->pribits <=3D 8); =20 - /* - * The GICv3 has separate ID register fields for virtual priority - * and preemption bit values, but only a single ID register field - * for the physical priority bits. The preemption bit count is - * always the same as the priority bit count, except that 8 bits - * of priority means 7 preemption bits. We precalculate the - * preemption bits because it simplifies the code and makes the - * parallels between the virtual and physical bits of the GIC - * a bit clearer. - */ - cs->prebits =3D cs->pribits; - if (cs->prebits =3D=3D 8) { - cs->prebits--; - } - /* - * Check that CPU code defining pribits didn't violate - * architectural constraints our implementation relies on. - */ - g_assert(cs->pribits >=3D 4 && cs->pribits <=3D 8); + /* + * gicv3_cpuif_reginfo[] defines ICC_AP*R0_EL1; add definitions + * for ICC_AP*R{1,2,3}_EL1 if the prebits value requires them. + */ + if (gcs->prebits >=3D 6) { + define_arm_cp_regs(cpu, gicv3_cpuif_icc_apxr1_reginfo); + } + if (gcs->prebits =3D=3D 7) { + define_arm_cp_regs(cpu, gicv3_cpuif_icc_apxr23_reginfo); + } =20 - /* - * gicv3_cpuif_reginfo[] defines ICC_AP*R0_EL1; add definitions - * for ICC_AP*R{1,2,3}_EL1 if the prebits value requires them. - */ - if (cs->prebits >=3D 6) { - define_arm_cp_regs(cpu, gicv3_cpuif_icc_apxr1_reginfo); - } - if (cs->prebits =3D=3D 7) { - define_arm_cp_regs(cpu, gicv3_cpuif_icc_apxr23_reginfo); - } + if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { + int j; =20 - if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { - int j; + gcs->num_list_regs =3D cpu->gic_num_lrs ?: 4; + gcs->vpribits =3D cpu->gic_vpribits ?: 5; + gcs->vprebits =3D cpu->gic_vprebits ?: 5; =20 - cs->num_list_regs =3D cpu->gic_num_lrs ?: 4; - cs->vpribits =3D cpu->gic_vpribits ?: 5; - cs->vprebits =3D cpu->gic_vprebits ?: 5; =20 - /* Check against architectural constraints: getting these - * wrong would be a bug in the CPU code defining these, - * and the implementation relies on them holding. - */ - g_assert(cs->vprebits <=3D cs->vpribits); - g_assert(cs->vprebits >=3D 5 && cs->vprebits <=3D 7); - g_assert(cs->vpribits >=3D 5 && cs->vpribits <=3D 8); + /* Check against architectural constraints: getting these + * wrong would be a bug in the CPU code defining these, + * and the implementation relies on them holding. + */ + g_assert(gcs->vprebits <=3D gcs->vpribits); + g_assert(gcs->vprebits >=3D 5 && gcs->vprebits <=3D 7); + g_assert(gcs->vpribits >=3D 5 && gcs->vpribits <=3D 8); =20 - define_arm_cp_regs(cpu, gicv3_cpuif_hcr_reginfo); + define_arm_cp_regs(cpu, gicv3_cpuif_hcr_reginfo); =20 - for (j =3D 0; j < cs->num_list_regs; j++) { - /* Note that the AArch64 LRs are 64-bit; the AArch32 LRs - * are split into two cp15 regs, LR (the low part, with the - * same encoding as the AArch64 LR) and LRC (the high part= ). - */ - ARMCPRegInfo lr_regset[] =3D { - { .name =3D "ICH_LRn_EL2", .state =3D ARM_CP_STATE_BOT= H, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, - .crm =3D 12 + (j >> 3), .opc2 =3D j & 7, - .type =3D ARM_CP_IO | ARM_CP_NO_RAW, - .nv2_redirect_offset =3D 0x400 + 8 * j, - .access =3D PL2_RW, - .readfn =3D ich_lr_read, - .writefn =3D ich_lr_write, - }, - { .name =3D "ICH_LRCn_EL2", .state =3D ARM_CP_STATE_AA= 32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 12, - .crm =3D 14 + (j >> 3), .opc2 =3D j & 7, - .type =3D ARM_CP_IO | ARM_CP_NO_RAW, - .access =3D PL2_RW, - .readfn =3D ich_lr_read, - .writefn =3D ich_lr_write, - }, - }; - define_arm_cp_regs(cpu, lr_regset); - } - if (cs->vprebits >=3D 6) { - define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr1_reginfo); - } - if (cs->vprebits =3D=3D 7) { - define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr23_reginfo); - } + for (j =3D 0; j < gcs->num_list_regs; j++) { + /* Note that the AArch64 LRs are 64-bit; the AArch32 LRs + * are split into two cp15 regs, LR (the low part, with the + * same encoding as the AArch64 LR) and LRC (the high part). + */ + ARMCPRegInfo lr_regset[] =3D { + { .name =3D "ICH_LRn_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, + .crm =3D 12 + (j >> 3), .opc2 =3D j & 7, + .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset =3D 0x400 + 8 * j, + .access =3D PL2_RW, + .readfn =3D ich_lr_read, + .writefn =3D ich_lr_write, + }, + { .name =3D "ICH_LRCn_EL2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 12, + .crm =3D 14 + (j >> 3), .opc2 =3D j & 7, + .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .access =3D PL2_RW, + .readfn =3D ich_lr_read, + .writefn =3D ich_lr_write, + }, + }; + define_arm_cp_regs(cpu, lr_regset); + } + if (gcs->vprebits >=3D 6) { + define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr1_reginfo); + } + if (gcs->vprebits =3D=3D 7) { + define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr23_reginfo); } if (tcg_enabled() || qtest_enabled()) { /* @@ -3177,7 +3172,7 @@ void gicv3_init_cpuif(GICv3State *s) * state only changes on EL changes involving EL2 or EL3, so f= or * the non-TCG case this is OK, as EL2 and EL3 can't exist. */ - arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, c= s); + arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, g= cs); } else { assert(!arm_feature(&cpu->env, ARM_FEATURE_EL2)); assert(!arm_feature(&cpu->env, ARM_FEATURE_EL3)); diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_com= mon.c index ff1239f65d..ef9eef3e01 100644 --- a/hw/intc/arm_gicv3_cpuif_common.c +++ b/hw/intc/arm_gicv3_cpuif_common.c @@ -20,3 +20,16 @@ void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *= s) =20 env->gicv3state =3D (void *)s; }; + +void gicv3_init_cpuif(GICv3State *s) +{ + ARMGICv3CommonClass *agcc =3D ARM_GICV3_COMMON_GET_CLASS(s); + int i; + + /* define and register `system registers` with the vCPU */ + for (i =3D 0; i < s->num_cpu; i++) { + if (gicv3_cpu_accessible(&s->cpu[i])) { + agcc->init_cpu_reginfo(s->cpu[i].cpu); + } + } +} diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 7e741ace50..3e1e97d830 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -796,6 +796,10 @@ static void vm_change_state_handler(void *opaque, bool= running, } } =20 +static void kvm_gicv3_init_cpu_reginfo(CPUState *cs) +{ + define_arm_cp_regs(ARM_CPU(cs), gicv3_cpuif_reginfo); +} =20 static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) { @@ -831,13 +835,8 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Er= ror **errp) =20 gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL); =20 - for (i =3D 0; i < s->num_cpu; i++) { - ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i)); - - if (gicv3_cpu_accessible(&s->cpu[i])) { - define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); - } - } + /* initialize vCPU interface */ + gicv3_init_cpuif(s); =20 /* Try to create the device via the device control API */ s->dev_fd =3D kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, f= alse); @@ -923,6 +922,7 @@ static void kvm_arm_gicv3_class_init(ObjectClass *klass= , void *data) =20 agcc->pre_save =3D kvm_arm_gicv3_get; agcc->post_load =3D kvm_arm_gicv3_put; + agcc->init_cpu_reginfo =3D kvm_gicv3_init_cpu_reginfo; device_class_set_parent_realize(dc, kvm_arm_gicv3_realize, &kgc->parent_realize); resettable_class_set_parent_phases(rc, NULL, kvm_arm_gicv3_reset_hold,= NULL, diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index bc9f518fe8..cc8edc499b 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -722,6 +722,7 @@ void gicv3_redist_vinvall(GICv3CPUState *cs, uint64_t v= ptaddr); =20 void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns); void gicv3_init_cpuif(GICv3State *s); +void gicv3_init_cpu_reginfo(CPUState *cs); =20 /** * gicv3_cpuif_update: diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 73d9088768..c19eb8d3d0 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -339,6 +339,7 @@ struct ARMGICv3CommonClass { =20 void (*pre_save)(GICv3State *s); void (*post_load)(GICv3State *s); + void (*init_cpu_reginfo)(CPUState *cs); }; =20 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, --=20 2.34.1