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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728432312; x=1729037112; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oOELs1GBJLtlq8nQGFT7BbF8Y02om3aScvqBsVkX7+Q=; b=O05Tx7zVQ0y2zGS9Q6GqBAi4Ceok4SaAAPjFEZdlHdbxA2DwQcLdA2KSF6ltKKcyik 2qOiQeIvxoa7S0yw+9D2/xijqAPr3+NoKw264v+K7wDmbrJ3KZaQDCQ9K8GeVZBQ/1hi E+We2sccOBiPa2ZLnMGjrbP8N5w0FleyWV74vY3UYqxs81SBfUPw7dG0PeorDyOWBT62 qher5a7I45cokEAl68NrWYV1+Qu+LioWPs9IIgXcBKqIe4YBWEovsnB0yTxF2ZYPr2A/ EUWAcOl8MhaL976Qp0fzqMXxEI+pnRoKLTFGR1lLsiNpQ8iitfVaJxaoy589q04XkD3E MQQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728432312; x=1729037112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oOELs1GBJLtlq8nQGFT7BbF8Y02om3aScvqBsVkX7+Q=; b=CgADoFpt/Q6AxxOwN1LkgNTKJgZWTQz1aOPHp9DTwlxntHo41R97XqCO7BrqcyAUu8 w0drRCKtanhjzPtoLdAMy6dbAeM4z4v3ksIT08s84U50tlydzPLId3H6b7paSjVqrrjW +J/xzmcA6O4kTANDVcw05t7ZfjZfzWrGK6qIOpyAE4uvxYzFEH1pu9QbgjpKE9flNFNk zcgQbIpBHLnWX+LGQtgxAQ/aZh7yZMCqLl1gbGJf2by30tlNzikzy/IokNvn+AD/xoGl 6p8ePsxyie7jAL6dq22v8jQPSEVsDPpU4zRrfWi5lGSjQPuLcd9kCWcXyX72/XucDzoa +9Ag== X-Gm-Message-State: AOJu0YyRYK2ek6IVKXaYTld6txgqzz8Hi6qSdHwg16SwVgme4gg77nSG mlUdwuIw/ruh7PzterEi8uHDV8zWFdi8x7zK37FhG9mn5E2YZ+eLjklDryUtAcsE+AvKfZGkM5K g X-Google-Smtp-Source: AGHT+IGdLlh7lpqvQhrMnt+h4KRJVDHjJLBqhH4OV1XyMKMzeUf8I/qGPJ2X48D5Sn4234GTGJ8pPw== X-Received: by 2002:a17:902:ce91:b0:20b:54e5:e822 with SMTP id d9443c01a7336-20c6377b24fmr8881225ad.21.1728432312463; Tue, 08 Oct 2024 17:05:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH v3 18/20] target/arm: Move device detection earlier in get_phys_addr_lpae Date: Tue, 8 Oct 2024 17:04:51 -0700 Message-ID: <20241009000453.315652-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1728432368802116600 Content-Type: text/plain; charset="utf-8" Determine cache attributes, and thence Device vs Normal memory, earlier in the function. We have an existing regime_is_stage2 if block into which this can be slotted. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 49 ++++++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 238b2c92a9..0a1a820362 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2029,8 +2029,20 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, xn =3D extract64(attrs, 53, 2); result->f.prot =3D get_S2prot(env, ap, xn, ptw->in_s1_is_el0); } + + result->cacheattrs.is_s2_format =3D true; + result->cacheattrs.attrs =3D extract32(attrs, 2, 4); + /* + * Security state does not really affect HCR_EL2.FWB; + * we only need to filter FWB for aa32 or other FEAT. + */ + device =3D S2_attrs_are_device(arm_hcr_el2_eff(env), + result->cacheattrs.attrs); } else { int nse, ns =3D extract32(attrs, 5, 1); + uint8_t attrindx; + uint64_t mair; + switch (out_space) { case ARMSS_Root: /* @@ -2102,6 +2114,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, */ result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, xn, pxn, result->f.attrs.space, out_space); + + /* Index into MAIR registers for cache attributes */ + attrindx =3D extract32(attrs, 2, 3); + mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; + assert(attrindx <=3D 7); + result->cacheattrs.is_s2_format =3D false; + result->cacheattrs.attrs =3D extract64(mair, attrindx * 8, 8); + + /* When in aarch64 mode, and BTI is enabled, remember GP in the TL= B. */ + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { + result->f.extra.arm.guarded =3D extract64(attrs, 50, 1); /* GP= */ + } + device =3D S1_attrs_are_device(result->cacheattrs.attrs); } =20 if (!(result->f.prot & (1 << access_type))) { @@ -2131,30 +2156,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, result->f.attrs.space =3D out_space; result->f.attrs.secure =3D arm_space_is_secure(out_space); =20 - if (regime_is_stage2(mmu_idx)) { - result->cacheattrs.is_s2_format =3D true; - result->cacheattrs.attrs =3D extract32(attrs, 2, 4); - /* - * Security state does not really affect HCR_EL2.FWB; - * we only need to filter FWB for aa32 or other FEAT. - */ - device =3D S2_attrs_are_device(arm_hcr_el2_eff(env), - result->cacheattrs.attrs); - } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx =3D extract32(attrs, 2, 3); - uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <=3D 7); - result->cacheattrs.is_s2_format =3D false; - result->cacheattrs.attrs =3D extract64(mair, attrindx * 8, 8); - - /* When in aarch64 mode, and BTI is enabled, remember GP in the TL= B. */ - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { - result->f.extra.arm.guarded =3D extract64(attrs, 50, 1); /* GP= */ - } - device =3D S1_attrs_are_device(result->cacheattrs.attrs); - } - /* * Enable alignment checks on Device memory. * --=20 2.43.0