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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138cecf2sm60705105ad.104.2024.10.08.17.05.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 17:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728432306; x=1729037106; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iV2KSUuCTdEDpKpG+VIBV8pupsJQOA9ecDi8J+rVd34=; b=J3aKb9Iyi691KWz01n8GgVdmpzlRcXM+e6yLl6g0beKQjo1nTAtVTe/0+a35GJUV7Q SFilfrH2Zgee4yBpV2DCNnAnf7Oc7677fnPC+I4lIUh3t50zIMa2q3Td460VsSJj/ON9 ZWNSBDB8X522LESZ20qnC6ouWpygRC+7j5sUtTmBBjP+hZ/GNIJF6slptyDQD17BHDFJ XWSoktcTWTmuDcfGPfwhKXZaLkZgy7rITynmGeCSl1rO18X42xfHQj0Obv6fB2b0Pm69 erTUU5jfuFDeW6CPH1ykzZ3bDmarPbqeLLAimIT8UV1Qtic4SI2RGTAxv1h6K53CH1Lb Io3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728432306; x=1729037106; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iV2KSUuCTdEDpKpG+VIBV8pupsJQOA9ecDi8J+rVd34=; b=roBYGVDvoqTyz0J7fPSoBIXyUS3NT75DwRNKaRu4J2SkHsbxEv2Z+L4crx7Mjzf0NL glLT9XuEa79uu2RbmTnFLbiTcRCxXakyBXKP/TQOYYGYVSOygVRVHCEA5WWXAIyioEdR PnZahY/xL/SRHjWZ7hX3wZSJwTDqfKCF0C8IsJScdNM4ajROckoEydSjHV91jDeOh9CP I58QWi7D1ZaVuiy6bzGiM/IYC2hqG5/ggcMIuKwK8LM9LupZVlgKfUUCyEDnAL353Rau NCXTnzpOrPzq3ZhXvJojxgjOQmSzJxOyhoO79MIi0LoSrKWQ3Q1W3Mn0lBYgOkvXlmoe 7qqw== X-Gm-Message-State: AOJu0YxDfKjtwms9fBB3/5O0zzUbc14pb9scjsFNoSGn1ECXzDLm+Q6u bIHup1QsnUS93D5iFu1R9C6zFKdgDKIkNmhabLkv6UDEHunsnUubJKPhYhcEnWyYm6LbX8WzI+H Y X-Google-Smtp-Source: AGHT+IEKU+69FGHaarUOvElg72DCHkm1xPG7wfOM2NLThus+mTJDQJLk8D0LtS7DglEQU4MbeYyvAA== X-Received: by 2002:a17:903:110c:b0:20c:5698:75cd with SMTP id d9443c01a7336-20c636eb2a7mr13032315ad.2.1728432306088; Tue, 08 Oct 2024 17:05:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH v3 11/20] target/hppa: Implement TCGCPUOps.tlb_fill_align Date: Tue, 8 Oct 2024 17:04:44 -0700 Message-ID: <20241009000453.315652-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009000453.315652-1-richard.henderson@linaro.org> References: <20241009000453.315652-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1728432546201116600 Content-Type: text/plain; charset="utf-8" Convert hppa_cpu_tlb_fill to hppa_cpu_tlb_fill_align so that we can recognize alignment exceptions in the correct priority order. Resolves: https://bugzilla.kernel.org/show_bug.cgi?id=3D219339 Signed-off-by: Richard Henderson Reviewed-by: Helge Deller Tested-by: Helge Deller --- target/hppa/cpu.h | 6 +++--- target/hppa/cpu.c | 2 +- target/hppa/mem_helper.c | 21 ++++++++++++--------- 3 files changed, 16 insertions(+), 13 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 526855f982..e45ba50a59 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -363,9 +363,9 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); void hppa_ptlbe(CPUHPPAState *env); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled= ); -bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr add= r, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t = ra); void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 7cf2e2f266..c38439c180 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -226,7 +226,7 @@ static const TCGCPUOps hppa_tcg_ops =3D { .restore_state_to_opc =3D hppa_restore_state_to_opc, =20 #ifndef CONFIG_USER_ONLY - .tlb_fill =3D hppa_cpu_tlb_fill, + .tlb_fill_align =3D hppa_cpu_tlb_fill_align, .cpu_exec_interrupt =3D hppa_cpu_exec_interrupt, .cpu_exec_halt =3D hppa_cpu_has_work, .do_interrupt =3D hppa_cpu_do_interrupt, diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index d38054da8a..b8c3e55170 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -424,12 +424,11 @@ void hppa_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, } } =20 -bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, - MMUAccessType type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr add= r, + MMUAccessType type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t = ra) { - HPPACPU *cpu =3D HPPA_CPU(cs); - CPUHPPAState *env =3D &cpu->env; + CPUHPPAState *env =3D cpu_env(cs); int prot, excp, a_prot; hwaddr phys; =20 @@ -445,7 +444,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int si= ze, break; } =20 - excp =3D hppa_get_physical_address(env, addr, mmu_idx, a_prot, 0, + excp =3D hppa_get_physical_address(env, addr, mmu_idx, a_prot, memop, &phys, &prot); if (unlikely(excp >=3D 0)) { if (probe) { @@ -454,7 +453,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int si= ze, trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx); =20 /* Failure. Raise the indicated exception. */ - raise_exception_with_ior(env, excp, retaddr, addr, + raise_exception_with_ior(env, excp, ra, addr, MMU_IDX_MMU_DISABLED(mmu_idx)); } =20 @@ -468,8 +467,12 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int s= ize, * the large page protection mask. We do not require this, * because we record the large page here in the hppa tlb. */ - tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, - prot, mmu_idx, TARGET_PAGE_SIZE); + memset(out, 0, sizeof(*out)); + out->phys_addr =3D phys; + out->prot =3D prot; + out->attrs =3D MEMTXATTRS_UNSPECIFIED; + out->lg_page_size =3D TARGET_PAGE_BITS; + return true; } =20 --=20 2.43.0