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Wed, 09 Oct 2024 16:09:10 -0700 (PDT) From: Atish Patra Date: Wed, 09 Oct 2024 16:09:04 -0700 Subject: [PATCH RFC 06/10] target/riscv: Define PMU event related structures MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-pmu_event_machine-v1-6-dcbd7a60e3ba@rivosinc.com> References: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alexei.filippov@syntacore.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=atishp@rivosinc.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728515477447116600 Signed-off-by: Atish Patra --- target/riscv/cpu.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2ac391a7cf74..53426710f73e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -189,6 +189,28 @@ typedef struct PMUFixedCtrState { uint64_t counter_virt_prev[2]; } PMUFixedCtrState; =20 +typedef uint64_t (*PMU_EVENT_CYCLE_FUNC)(RISCVCPU *); +typedef uint64_t (*PMU_EVENT_INSTRET_FUNC)(RISCVCPU *); +typedef uint64_t (*PMU_EVENT_TLB_FUNC)(RISCVCPU *, MMUAccessType access_ty= pe); + +typedef struct PMUEventInfo { + /* Event ID (BIT [0:55] valid) */ + uint64_t event_id; + /* Supported hpmcounters for this event */ + uint32_t counter_mask; + /* Bitmask of valid event bits */ + uint64_t event_mask; +} PMUEventInfo; + +typedef struct PMUEventFunc { + /* Get the ID of the event that can monitor cycles */ + PMU_EVENT_CYCLE_FUNC get_cycle_id; + /* Get the ID of the event that can monitor cycles */ + PMU_EVENT_INSTRET_FUNC get_intstret_id; + /* Get the ID of the event that can monitor TLB events*/ + PMU_EVENT_TLB_FUNC get_tlb_access_id; +} PMUEventFunc; + struct CPUArchState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ @@ -386,6 +408,9 @@ struct CPUArchState { target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; =20 PMUFixedCtrState pmu_fixed_ctrs[2]; + PMUEventInfo *pmu_events; + PMUEventFunc pmu_efuncs; + int num_pmu_events; =20 target_ulong sscratch; target_ulong mscratch; --=20 2.34.1