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Wed, 09 Oct 2024 16:09:08 -0700 (PDT) From: Atish Patra Date: Wed, 09 Oct 2024 16:09:03 -0700 Subject: [PATCH RFC 05/10] target/riscv: Rename the PMU events MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-pmu_event_machine-v1-5-dcbd7a60e3ba@rivosinc.com> References: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alexei.filippov@syntacore.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=atishp@rivosinc.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728515455236116600 The current PMU events are defined by SBI PMU specification. As there is no standard event encoding scheme, Virt machine chooses to use the SBI PMU encoding. A platform may choose to implement a different event encoding scheme completely. Rename the event names to reflect the reality. No functional changes introduced. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 26 +++++++++++++++----- target/riscv/cpu_helper.c | 8 +++--- target/riscv/pmu.c | 62 ++++++++++++++++++-------------------------= ---- target/riscv/pmu.h | 2 +- 4 files changed, 48 insertions(+), 50 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 97e408b91219..2ac391a7cf74 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -820,14 +820,28 @@ enum { /* * The event id are encoded based on the encoding specified in the * SBI specification v0.3 + * + * The event encoding is specified in the SBI specification + * Event idx is a 20bits wide number encoded as follows: + * event_idx[19:16] =3D type + * event_idx[15:0] =3D code + * The code field in cache events are encoded as follows: + * event_idx.code[15:3] =3D cache_id + * event_idx.code[2:1] =3D op_id + * event_idx.code[0:0] =3D result_id */ =20 -enum riscv_pmu_event_idx { - RISCV_PMU_EVENT_HW_CPU_CYCLES =3D 0x01, - RISCV_PMU_EVENT_HW_INSTRUCTIONS =3D 0x02, - RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS =3D 0x10019, - RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS =3D 0x1001B, - RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, +enum virt_pmu_event_idx { + /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */ + VIRT_PMU_EVENT_HW_CPU_CYCLES =3D 0x01, + /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */ + VIRT_PMU_EVENT_HW_INSTRUCTIONS =3D 0x02, + /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */ + VIRT_PMU_EVENT_CACHE_DTLB_READ_MISS =3D 0x10019, + /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */ + VIRT_PMU_EVENT_CACHE_DTLB_WRITE_MISS =3D 0x1001B, + /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */ + VIRT_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, }; =20 /* used by tcg/tcg-cpu.c*/ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 203c0a92ab75..0f1655a221bd 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1295,17 +1295,17 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, va= ddr addr, =20 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) { - enum riscv_pmu_event_idx pmu_event_type; + enum virt_pmu_event_idx pmu_event_type; =20 switch (access_type) { case MMU_INST_FETCH: - pmu_event_type =3D RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; + pmu_event_type =3D VIRT_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; break; case MMU_DATA_LOAD: - pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; + pmu_event_type =3D VIRT_PMU_EVENT_CACHE_DTLB_READ_MISS; break; case MMU_DATA_STORE: - pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; + pmu_event_type =3D VIRT_PMU_EVENT_CACHE_DTLB_WRITE_MISS; break; default: return; diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 2531d4f1a9c1..c436b08d1043 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -38,40 +38,24 @@ void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cm= ask, char *pmu_name) { uint32_t fdt_event_ctr_map[15] =3D {}; =20 - /* - * The event encoding is specified in the SBI specification - * Event idx is a 20bits wide number encoded as follows: - * event_idx[19:16] =3D type - * event_idx[15:0] =3D code - * The code field in cache events are encoded as follows: - * event_idx.code[15:3] =3D cache_id - * event_idx.code[2:1] =3D op_id - * event_idx.code[0:0] =3D result_id - */ - - /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */ - fdt_event_ctr_map[0] =3D cpu_to_be32(0x00000001); - fdt_event_ctr_map[1] =3D cpu_to_be32(0x00000001); + fdt_event_ctr_map[0] =3D cpu_to_be32(VIRT_PMU_EVENT_HW_CPU_CYCLES); + fdt_event_ctr_map[1] =3D cpu_to_be32(VIRT_PMU_EVENT_HW_CPU_CYCLES); fdt_event_ctr_map[2] =3D cpu_to_be32(cmask | 1 << 0); =20 - /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */ - fdt_event_ctr_map[3] =3D cpu_to_be32(0x00000002); - fdt_event_ctr_map[4] =3D cpu_to_be32(0x00000002); + fdt_event_ctr_map[3] =3D cpu_to_be32(VIRT_PMU_EVENT_HW_INSTRUCTIONS); + fdt_event_ctr_map[4] =3D cpu_to_be32(VIRT_PMU_EVENT_HW_INSTRUCTIONS); fdt_event_ctr_map[5] =3D cpu_to_be32(cmask | 1 << 2); =20 - /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */ - fdt_event_ctr_map[6] =3D cpu_to_be32(0x00010019); - fdt_event_ctr_map[7] =3D cpu_to_be32(0x00010019); + fdt_event_ctr_map[6] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_DTLB_READ_MIS= S); + fdt_event_ctr_map[7] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_DTLB_READ_MIS= S); fdt_event_ctr_map[8] =3D cpu_to_be32(cmask); =20 - /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */ - fdt_event_ctr_map[9] =3D cpu_to_be32(0x0001001B); - fdt_event_ctr_map[10] =3D cpu_to_be32(0x0001001B); + fdt_event_ctr_map[9] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_DTLB_WRITE_MI= SS); + fdt_event_ctr_map[10] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_DTLB_WRITE_M= ISS); fdt_event_ctr_map[11] =3D cpu_to_be32(cmask); =20 - /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */ - fdt_event_ctr_map[12] =3D cpu_to_be32(0x00010021); - fdt_event_ctr_map[13] =3D cpu_to_be32(0x00010021); + fdt_event_ctr_map[12] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_ITLB_PREFETC= H_MISS); + fdt_event_ctr_map[13] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_ITLB_PREFETC= H_MISS); fdt_event_ctr_map[14] =3D cpu_to_be32(cmask); =20 /* This a OpenSBI specific DT property documented in OpenSBI docs */ @@ -290,7 +274,7 @@ void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, ta= rget_ulong newpriv, riscv_pmu_icount_update_priv(env, newpriv, new_virt); } =20 -int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) +int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum virt_pmu_event_idx event_idx) { uint32_t ctr_idx; int ret; @@ -329,7 +313,7 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *= env, } =20 cpu =3D env_archcpu(env); - if (!riscv_pmu_htable_lookup(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS, + if (!riscv_pmu_htable_lookup(cpu, VIRT_PMU_EVENT_HW_INSTRUCTIONS, &ctr_idx)) { return false; } @@ -348,7 +332,7 @@ bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, u= int32_t target_ctr) } =20 cpu =3D env_archcpu(env); - if (!riscv_pmu_htable_lookup(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES, + if (!riscv_pmu_htable_lookup(cpu, VIRT_PMU_EVENT_HW_CPU_CYCLES, &ctr_idx)) { return false; } @@ -406,11 +390,11 @@ int riscv_pmu_update_event_map(CPURISCVState *env, ui= nt64_t value, } =20 switch (event_idx) { - case RISCV_PMU_EVENT_HW_CPU_CYCLES: - case RISCV_PMU_EVENT_HW_INSTRUCTIONS: - case RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS: - case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS: - case RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS: + case VIRT_PMU_EVENT_HW_CPU_CYCLES: + case VIRT_PMU_EVENT_HW_INSTRUCTIONS: + case VIRT_PMU_EVENT_CACHE_DTLB_READ_MISS: + case VIRT_PMU_EVENT_CACHE_DTLB_WRITE_MISS: + case VIRT_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS: break; default: /* We don't support any raw events right now */ @@ -464,7 +448,7 @@ static bool pmu_hpmevent_set_of_if_clear(CPURISCVState = *env, uint32_t ctr_idx) } =20 static void pmu_timer_trigger_irq(RISCVCPU *cpu, - enum riscv_pmu_event_idx evt_idx) + enum virt_pmu_event_idx evt_idx) { uint32_t ctr_idx; CPURISCVState *env =3D &cpu->env; @@ -473,8 +457,8 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu, uint64_t curr_ctr_val, curr_ctrh_val; uint64_t ctr_val; =20 - if (evt_idx !=3D RISCV_PMU_EVENT_HW_CPU_CYCLES && - evt_idx !=3D RISCV_PMU_EVENT_HW_INSTRUCTIONS) { + if (evt_idx !=3D VIRT_PMU_EVENT_HW_CPU_CYCLES && + evt_idx !=3D VIRT_PMU_EVENT_HW_INSTRUCTIONS) { return; } =20 @@ -533,8 +517,8 @@ void riscv_pmu_timer_cb(void *priv) RISCVCPU *cpu =3D priv; =20 /* Timer event was triggered only for these events */ - pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES); - pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS); + pmu_timer_trigger_irq(cpu, VIRT_PMU_EVENT_HW_CPU_CYCLES); + pmu_timer_trigger_irq(cpu, VIRT_PMU_EVENT_HW_INSTRUCTIONS); } =20 int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr= _idx) diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 3853d0e2629e..75a22d596b69 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -30,7 +30,7 @@ void riscv_pmu_timer_cb(void *priv); void riscv_pmu_init(RISCVCPU *cpu, Error **errp); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); -int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); +int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum virt_pmu_event_idx event_idx); void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name= ); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); --=20 2.34.1