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Wed, 09 Oct 2024 16:09:07 -0700 (PDT) From: Atish Patra Date: Wed, 09 Oct 2024 16:09:02 -0700 Subject: [PATCH RFC 04/10] target/riscv: Use uint64 instead of uint as key MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-pmu_event_machine-v1-4-dcbd7a60e3ba@rivosinc.com> References: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alexei.filippov@syntacore.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=atishp@rivosinc.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728515443275116600 The event ID can be a upto 56 bit value when sscofpmf is implemented. Change the event to counter hashtable to store the keys as 64 bit value instead of uint. Signed-off-by: Atish Patra --- target/riscv/pmu.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 21377518f4e0..2531d4f1a9c1 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -265,14 +265,14 @@ static void riscv_pmu_cycle_update_priv(CPURISCVState= *env, counter_arr[env->priv] +=3D delta; } =20 -static bool riscv_pmu_htable_lookup(RISCVCPU *cpu, uint32_t key, +static bool riscv_pmu_htable_lookup(RISCVCPU *cpu, uint64_t key, uint32_t *value) { GHashTable *table =3D cpu->pmu_event_ctr_map; gpointer val_ptr; =20 pthread_rwlock_rdlock(&cpu->pmu_map_lock); - gpointer val_ptr =3D g_hash_table_lookup(table, GUINT_TO_POINTER(key)); + val_ptr =3D g_hash_table_lookup(table, &key); if (!val_ptr) { pthread_rwlock_unlock(&cpu->pmu_map_lock); return false; @@ -378,9 +378,10 @@ static int64_t pmu_icount_ticks_to_ns(int64_t value) int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx) { - uint32_t event_idx; + uint64_t event_idx; RISCVCPU *cpu =3D env_archcpu(env); uint32_t mapped_ctr_idx; + gint64 *eid_ptr; =20 if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map)= { return -1; @@ -415,8 +416,10 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uin= t64_t value, /* We don't support any raw events right now */ return -1; } + eid_ptr =3D g_new(gint64, 1); + *eid_ptr =3D event_idx; pthread_rwlock_wrlock(&cpu->pmu_map_lock); - g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx= ), + g_hash_table_insert(cpu->pmu_event_ctr_map, eid_ptr, GUINT_TO_POINTER(ctr_idx)); pthread_rwlock_unlock(&cpu->pmu_map_lock); =20 @@ -597,7 +600,8 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) return; } =20 - cpu->pmu_event_ctr_map =3D g_hash_table_new(g_direct_hash, g_direct_eq= ual); + cpu->pmu_event_ctr_map =3D g_hash_table_new_full(g_int64_hash, g_int64= _equal, + g_free, NULL); if (!cpu->pmu_event_ctr_map) { error_setg(errp, "Unable to allocate PMU event hash table"); return; --=20 2.34.1