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Wed, 09 Oct 2024 16:09:06 -0700 (PDT) From: Atish Patra Date: Wed, 09 Oct 2024 16:09:01 -0700 Subject: [PATCH RFC 03/10] target/riscv: Protect the hashtable modifications with a lock MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-pmu_event_machine-v1-3-dcbd7a60e3ba@rivosinc.com> References: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alexei.filippov@syntacore.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=atishp@rivosinc.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728515467369116600 Add a read/write lock to protect the hashtable access operations in multi-threaded scenario. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + target/riscv/pmu.c | 10 +++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a63a29744c26..97e408b91219 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -496,6 +496,7 @@ struct ArchCPU { uint32_t pmu_avail_ctrs; /* Mapping of events to counters */ GHashTable *pmu_event_ctr_map; + pthread_rwlock_t pmu_map_lock; const GPtrArray *decoders; }; =20 diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index a88c321a6cad..21377518f4e0 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -271,12 +271,15 @@ static bool riscv_pmu_htable_lookup(RISCVCPU *cpu, ui= nt32_t key, GHashTable *table =3D cpu->pmu_event_ctr_map; gpointer val_ptr; =20 - val_ptr =3D g_hash_table_lookup(table, GUINT_TO_POINTER(key)); + pthread_rwlock_rdlock(&cpu->pmu_map_lock); + gpointer val_ptr =3D g_hash_table_lookup(table, GUINT_TO_POINTER(key)); if (!val_ptr) { + pthread_rwlock_unlock(&cpu->pmu_map_lock); return false; } =20 *value =3D GPOINTER_TO_UINT(val_ptr); + pthread_rwlock_unlock(&cpu->pmu_map_lock); return true; } =20 @@ -388,9 +391,11 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uin= t64_t value, * mapping. */ if (!value) { + pthread_rwlock_wrlock(&cpu->pmu_map_lock); g_hash_table_foreach_remove(cpu->pmu_event_ctr_map, pmu_remove_event_map, GUINT_TO_POINTER(ctr_idx)); + pthread_rwlock_unlock(&cpu->pmu_map_lock); return 0; } =20 @@ -410,8 +415,10 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uin= t64_t value, /* We don't support any raw events right now */ return -1; } + pthread_rwlock_wrlock(&cpu->pmu_map_lock); g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx= ), GUINT_TO_POINTER(ctr_idx)); + pthread_rwlock_unlock(&cpu->pmu_map_lock); =20 return 0; } @@ -597,4 +604,5 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) } =20 cpu->pmu_avail_ctrs =3D cpu->cfg.pmu_mask; + pthread_rwlock_init(&cpu->pmu_map_lock, NULL); } --=20 2.34.1