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Wed, 09 Oct 2024 16:09:04 -0700 (PDT) From: Atish Patra Date: Wed, 09 Oct 2024 16:08:59 -0700 Subject: [PATCH RFC 01/10] target/riscv: Fix the hpmevent mask MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-pmu_event_machine-v1-1-dcbd7a60e3ba@rivosinc.com> References: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alexei.filippov@syntacore.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=atishp@rivosinc.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728515405094116600 As per the latest privilege specification v1.13[1], the sscofpmf only reserves first 8 bits of hpmeventX. Update the corresponding masks accordingly. [1]https://github.com/riscv/riscv-isa-manual/issues/1578 Signed-off-by: Atish Patra --- target/riscv/cpu_bits.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7e3f629356ba..a7b8bcbd0148 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -938,8 +938,8 @@ typedef enum RISCVException { MHPMEVENTH_BIT_VSINH | \ MHPMEVENTH_BIT_VUINH) =20 -#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) -#define MHPMEVENT_IDX_MASK 0xFFFFF +#define MHPMEVENT_SSCOF_MASK 0xFF00000000000000ULL +#define MHPMEVENT_IDX_MASK (~MHPMEVENT_SSCOF_MASK) #define MHPMEVENT_SSCOF_RESVD 16 =20 /* JVT CSR bits */ --=20 2.34.1 From nobody Sat Nov 23 21:19:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-pmu_event_machine-v1-2-dcbd7a60e3ba@rivosinc.com> References: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alexei.filippov@syntacore.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=atishp@rivosinc.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728515479335116600 The pmu implementation requires hashtable lookup operation sprinkled through the file. Add a helper function that allows to consolidate the implementation and extend it in the future easily. Signed-off-by: Atish Patra --- target/riscv/pmu.c | 56 ++++++++++++++++++++++++++------------------------= ---- 1 file changed, 27 insertions(+), 29 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index e05ab067d2f2..a88c321a6cad 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -265,6 +265,21 @@ static void riscv_pmu_cycle_update_priv(CPURISCVState = *env, counter_arr[env->priv] +=3D delta; } =20 +static bool riscv_pmu_htable_lookup(RISCVCPU *cpu, uint32_t key, + uint32_t *value) +{ + GHashTable *table =3D cpu->pmu_event_ctr_map; + gpointer val_ptr; + + val_ptr =3D g_hash_table_lookup(table, GUINT_TO_POINTER(key)); + if (!val_ptr) { + return false; + } + + *value =3D GPOINTER_TO_UINT(val_ptr); + return true; +} + void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, bool new_virt) { @@ -277,18 +292,15 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_= event_idx event_idx) uint32_t ctr_idx; int ret; CPURISCVState *env =3D &cpu->env; - gpointer value; =20 if (!cpu->cfg.pmu_mask) { return 0; } - value =3D g_hash_table_lookup(cpu->pmu_event_ctr_map, - GUINT_TO_POINTER(event_idx)); - if (!value) { + + if (!riscv_pmu_htable_lookup(cpu, event_idx, &ctr_idx)) { return -1; } =20 - ctr_idx =3D GPOINTER_TO_UINT(value); if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) { return -1; } @@ -306,7 +318,6 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *= env, uint32_t target_ctr) { RISCVCPU *cpu; - uint32_t event_idx; uint32_t ctr_idx; =20 /* Fixed instret counter */ @@ -315,14 +326,8 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState = *env, } =20 cpu =3D env_archcpu(env); - if (!cpu->pmu_event_ctr_map) { - return false; - } - - event_idx =3D RISCV_PMU_EVENT_HW_INSTRUCTIONS; - ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, - GUINT_TO_POINTER(event_idx))); - if (!ctr_idx) { + if (!riscv_pmu_htable_lookup(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS, + &ctr_idx)) { return false; } =20 @@ -332,7 +337,6 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *= env, bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr) { RISCVCPU *cpu; - uint32_t event_idx; uint32_t ctr_idx; =20 /* Fixed mcycle counter */ @@ -341,16 +345,8 @@ bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, = uint32_t target_ctr) } =20 cpu =3D env_archcpu(env); - if (!cpu->pmu_event_ctr_map) { - return false; - } - - event_idx =3D RISCV_PMU_EVENT_HW_CPU_CYCLES; - ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, - GUINT_TO_POINTER(event_idx))); - - /* Counter zero is not used for event_ctr_map */ - if (!ctr_idx) { + if (!riscv_pmu_htable_lookup(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES, + &ctr_idx)) { return false; } =20 @@ -381,6 +377,7 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint= 64_t value, { uint32_t event_idx; RISCVCPU *cpu =3D env_archcpu(env); + uint32_t mapped_ctr_idx; =20 if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map)= { return -1; @@ -398,8 +395,7 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint= 64_t value, } =20 event_idx =3D value & MHPMEVENT_IDX_MASK; - if (g_hash_table_lookup(cpu->pmu_event_ctr_map, - GUINT_TO_POINTER(event_idx))) { + if (riscv_pmu_htable_lookup(cpu, event_idx, &mapped_ctr_idx)) { return 0; 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Wed, 09 Oct 2024 16:09:06 -0700 (PDT) From: Atish Patra Date: Wed, 09 Oct 2024 16:09:01 -0700 Subject: [PATCH RFC 03/10] target/riscv: Protect the hashtable modifications with a lock MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-pmu_event_machine-v1-3-dcbd7a60e3ba@rivosinc.com> References: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alexei.filippov@syntacore.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; 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Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + target/riscv/pmu.c | 10 +++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a63a29744c26..97e408b91219 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -496,6 +496,7 @@ struct ArchCPU { uint32_t pmu_avail_ctrs; /* Mapping of events to counters */ GHashTable *pmu_event_ctr_map; + pthread_rwlock_t pmu_map_lock; const GPtrArray *decoders; }; =20 diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index a88c321a6cad..21377518f4e0 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -271,12 +271,15 @@ static bool riscv_pmu_htable_lookup(RISCVCPU *cpu, ui= nt32_t key, GHashTable *table =3D cpu->pmu_event_ctr_map; gpointer val_ptr; =20 - val_ptr =3D g_hash_table_lookup(table, GUINT_TO_POINTER(key)); + pthread_rwlock_rdlock(&cpu->pmu_map_lock); + gpointer val_ptr =3D g_hash_table_lookup(table, GUINT_TO_POINTER(key)); if (!val_ptr) { + pthread_rwlock_unlock(&cpu->pmu_map_lock); return false; } =20 *value =3D GPOINTER_TO_UINT(val_ptr); + pthread_rwlock_unlock(&cpu->pmu_map_lock); return true; } =20 @@ -388,9 +391,11 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uin= t64_t value, * mapping. */ if (!value) { + pthread_rwlock_wrlock(&cpu->pmu_map_lock); g_hash_table_foreach_remove(cpu->pmu_event_ctr_map, pmu_remove_event_map, GUINT_TO_POINTER(ctr_idx)); + pthread_rwlock_unlock(&cpu->pmu_map_lock); return 0; } =20 @@ -410,8 +415,10 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uin= t64_t value, /* We don't support any raw events right now */ return -1; } + pthread_rwlock_wrlock(&cpu->pmu_map_lock); g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx= ), GUINT_TO_POINTER(ctr_idx)); + pthread_rwlock_unlock(&cpu->pmu_map_lock); =20 return 0; } @@ -597,4 +604,5 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) } =20 cpu->pmu_avail_ctrs =3D cpu->cfg.pmu_mask; + pthread_rwlock_init(&cpu->pmu_map_lock, NULL); } --=20 2.34.1 From nobody Sat Nov 23 21:19:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 09 Oct 2024 16:09:07 -0700 (PDT) From: Atish Patra Date: Wed, 09 Oct 2024 16:09:02 -0700 Subject: [PATCH RFC 04/10] target/riscv: Use uint64 instead of uint as key MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-pmu_event_machine-v1-4-dcbd7a60e3ba@rivosinc.com> References: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alexei.filippov@syntacore.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=atishp@rivosinc.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728515443275116600 The event ID can be a upto 56 bit value when sscofpmf is implemented. Change the event to counter hashtable to store the keys as 64 bit value instead of uint. Signed-off-by: Atish Patra --- target/riscv/pmu.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 21377518f4e0..2531d4f1a9c1 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -265,14 +265,14 @@ static void riscv_pmu_cycle_update_priv(CPURISCVState= *env, counter_arr[env->priv] +=3D delta; } =20 -static bool riscv_pmu_htable_lookup(RISCVCPU *cpu, uint32_t key, +static bool riscv_pmu_htable_lookup(RISCVCPU *cpu, uint64_t key, uint32_t *value) { GHashTable *table =3D cpu->pmu_event_ctr_map; gpointer val_ptr; =20 pthread_rwlock_rdlock(&cpu->pmu_map_lock); - gpointer val_ptr =3D g_hash_table_lookup(table, GUINT_TO_POINTER(key)); + val_ptr =3D g_hash_table_lookup(table, &key); if (!val_ptr) { pthread_rwlock_unlock(&cpu->pmu_map_lock); return false; @@ -378,9 +378,10 @@ static int64_t pmu_icount_ticks_to_ns(int64_t value) int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx) { - uint32_t event_idx; + uint64_t event_idx; RISCVCPU *cpu =3D env_archcpu(env); uint32_t mapped_ctr_idx; + gint64 *eid_ptr; =20 if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map)= { return -1; @@ -415,8 +416,10 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uin= t64_t value, /* We don't support any raw events right now */ return -1; } + eid_ptr =3D g_new(gint64, 1); + *eid_ptr =3D event_idx; pthread_rwlock_wrlock(&cpu->pmu_map_lock); - g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx= ), + g_hash_table_insert(cpu->pmu_event_ctr_map, eid_ptr, GUINT_TO_POINTER(ctr_idx)); pthread_rwlock_unlock(&cpu->pmu_map_lock); =20 @@ -597,7 +600,8 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) return; } =20 - cpu->pmu_event_ctr_map =3D g_hash_table_new(g_direct_hash, g_direct_eq= ual); + cpu->pmu_event_ctr_map =3D g_hash_table_new_full(g_int64_hash, g_int64= _equal, + g_free, NULL); if (!cpu->pmu_event_ctr_map) { error_setg(errp, "Unable to allocate PMU event hash table"); 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Wed, 09 Oct 2024 16:09:08 -0700 (PDT) From: Atish Patra Date: Wed, 09 Oct 2024 16:09:03 -0700 Subject: [PATCH RFC 05/10] target/riscv: Rename the PMU events MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-pmu_event_machine-v1-5-dcbd7a60e3ba@rivosinc.com> References: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alexei.filippov@syntacore.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=atishp@rivosinc.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728515455236116600 The current PMU events are defined by SBI PMU specification. As there is no standard event encoding scheme, Virt machine chooses to use the SBI PMU encoding. A platform may choose to implement a different event encoding scheme completely. Rename the event names to reflect the reality. No functional changes introduced. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 26 +++++++++++++++----- target/riscv/cpu_helper.c | 8 +++--- target/riscv/pmu.c | 62 ++++++++++++++++++-------------------------= ---- target/riscv/pmu.h | 2 +- 4 files changed, 48 insertions(+), 50 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 97e408b91219..2ac391a7cf74 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -820,14 +820,28 @@ enum { /* * The event id are encoded based on the encoding specified in the * SBI specification v0.3 + * + * The event encoding is specified in the SBI specification + * Event idx is a 20bits wide number encoded as follows: + * event_idx[19:16] =3D type + * event_idx[15:0] =3D code + * The code field in cache events are encoded as follows: + * event_idx.code[15:3] =3D cache_id + * event_idx.code[2:1] =3D op_id + * event_idx.code[0:0] =3D result_id */ =20 -enum riscv_pmu_event_idx { - RISCV_PMU_EVENT_HW_CPU_CYCLES =3D 0x01, - RISCV_PMU_EVENT_HW_INSTRUCTIONS =3D 0x02, - RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS =3D 0x10019, - RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS =3D 0x1001B, - RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, +enum virt_pmu_event_idx { + /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */ + VIRT_PMU_EVENT_HW_CPU_CYCLES =3D 0x01, + /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */ + VIRT_PMU_EVENT_HW_INSTRUCTIONS =3D 0x02, + /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */ + VIRT_PMU_EVENT_CACHE_DTLB_READ_MISS =3D 0x10019, + /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */ + VIRT_PMU_EVENT_CACHE_DTLB_WRITE_MISS =3D 0x1001B, + /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */ + VIRT_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, }; =20 /* used by tcg/tcg-cpu.c*/ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 203c0a92ab75..0f1655a221bd 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1295,17 +1295,17 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, va= ddr addr, =20 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) { - enum riscv_pmu_event_idx pmu_event_type; + enum virt_pmu_event_idx pmu_event_type; =20 switch (access_type) { case MMU_INST_FETCH: - pmu_event_type =3D RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; + pmu_event_type =3D VIRT_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; break; case MMU_DATA_LOAD: - pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; + pmu_event_type =3D VIRT_PMU_EVENT_CACHE_DTLB_READ_MISS; break; case MMU_DATA_STORE: - pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; + pmu_event_type =3D VIRT_PMU_EVENT_CACHE_DTLB_WRITE_MISS; break; default: return; diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 2531d4f1a9c1..c436b08d1043 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -38,40 +38,24 @@ void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cm= ask, char *pmu_name) { uint32_t fdt_event_ctr_map[15] =3D {}; =20 - /* - * The event encoding is specified in the SBI specification - * Event idx is a 20bits wide number encoded as follows: - * event_idx[19:16] =3D type - * event_idx[15:0] =3D code - * The code field in cache events are encoded as follows: - * event_idx.code[15:3] =3D cache_id - * event_idx.code[2:1] =3D op_id - * event_idx.code[0:0] =3D result_id - */ - - /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */ - fdt_event_ctr_map[0] =3D cpu_to_be32(0x00000001); - fdt_event_ctr_map[1] =3D cpu_to_be32(0x00000001); + fdt_event_ctr_map[0] =3D cpu_to_be32(VIRT_PMU_EVENT_HW_CPU_CYCLES); + fdt_event_ctr_map[1] =3D cpu_to_be32(VIRT_PMU_EVENT_HW_CPU_CYCLES); fdt_event_ctr_map[2] =3D cpu_to_be32(cmask | 1 << 0); =20 - /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */ - fdt_event_ctr_map[3] =3D cpu_to_be32(0x00000002); - fdt_event_ctr_map[4] =3D cpu_to_be32(0x00000002); + fdt_event_ctr_map[3] =3D cpu_to_be32(VIRT_PMU_EVENT_HW_INSTRUCTIONS); + fdt_event_ctr_map[4] =3D cpu_to_be32(VIRT_PMU_EVENT_HW_INSTRUCTIONS); fdt_event_ctr_map[5] =3D cpu_to_be32(cmask | 1 << 2); =20 - /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */ - fdt_event_ctr_map[6] =3D cpu_to_be32(0x00010019); - fdt_event_ctr_map[7] =3D cpu_to_be32(0x00010019); + fdt_event_ctr_map[6] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_DTLB_READ_MIS= S); + fdt_event_ctr_map[7] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_DTLB_READ_MIS= S); fdt_event_ctr_map[8] =3D cpu_to_be32(cmask); =20 - /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */ - fdt_event_ctr_map[9] =3D cpu_to_be32(0x0001001B); - fdt_event_ctr_map[10] =3D cpu_to_be32(0x0001001B); + fdt_event_ctr_map[9] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_DTLB_WRITE_MI= SS); + fdt_event_ctr_map[10] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_DTLB_WRITE_M= ISS); fdt_event_ctr_map[11] =3D cpu_to_be32(cmask); =20 - /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */ - fdt_event_ctr_map[12] =3D cpu_to_be32(0x00010021); - fdt_event_ctr_map[13] =3D cpu_to_be32(0x00010021); + fdt_event_ctr_map[12] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_ITLB_PREFETC= H_MISS); + fdt_event_ctr_map[13] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_ITLB_PREFETC= H_MISS); fdt_event_ctr_map[14] =3D cpu_to_be32(cmask); =20 /* This a OpenSBI specific DT property documented in OpenSBI docs */ @@ -290,7 +274,7 @@ void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, ta= rget_ulong newpriv, riscv_pmu_icount_update_priv(env, newpriv, new_virt); } =20 -int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) +int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum virt_pmu_event_idx event_idx) { uint32_t ctr_idx; int ret; @@ -329,7 +313,7 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *= env, } =20 cpu =3D env_archcpu(env); - if (!riscv_pmu_htable_lookup(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS, + if (!riscv_pmu_htable_lookup(cpu, VIRT_PMU_EVENT_HW_INSTRUCTIONS, &ctr_idx)) { return false; } @@ -348,7 +332,7 @@ bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, u= int32_t target_ctr) } =20 cpu =3D env_archcpu(env); - if (!riscv_pmu_htable_lookup(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES, + if (!riscv_pmu_htable_lookup(cpu, VIRT_PMU_EVENT_HW_CPU_CYCLES, &ctr_idx)) { return false; } @@ -406,11 +390,11 @@ int riscv_pmu_update_event_map(CPURISCVState *env, ui= nt64_t value, } =20 switch (event_idx) { - case RISCV_PMU_EVENT_HW_CPU_CYCLES: - case RISCV_PMU_EVENT_HW_INSTRUCTIONS: - case RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS: - case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS: - case RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS: + case VIRT_PMU_EVENT_HW_CPU_CYCLES: + case VIRT_PMU_EVENT_HW_INSTRUCTIONS: + case VIRT_PMU_EVENT_CACHE_DTLB_READ_MISS: + case VIRT_PMU_EVENT_CACHE_DTLB_WRITE_MISS: + case VIRT_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS: break; default: /* We don't support any raw events right now */ @@ -464,7 +448,7 @@ static bool pmu_hpmevent_set_of_if_clear(CPURISCVState = *env, uint32_t ctr_idx) } =20 static void pmu_timer_trigger_irq(RISCVCPU *cpu, - enum riscv_pmu_event_idx evt_idx) + enum virt_pmu_event_idx evt_idx) { uint32_t ctr_idx; CPURISCVState *env =3D &cpu->env; @@ -473,8 +457,8 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu, uint64_t curr_ctr_val, curr_ctrh_val; uint64_t ctr_val; =20 - if (evt_idx !=3D RISCV_PMU_EVENT_HW_CPU_CYCLES && - evt_idx !=3D RISCV_PMU_EVENT_HW_INSTRUCTIONS) { + if (evt_idx !=3D VIRT_PMU_EVENT_HW_CPU_CYCLES && + evt_idx !=3D VIRT_PMU_EVENT_HW_INSTRUCTIONS) { return; } =20 @@ -533,8 +517,8 @@ void riscv_pmu_timer_cb(void *priv) RISCVCPU *cpu =3D priv; =20 /* Timer event was triggered only for these events */ - pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES); - pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS); + pmu_timer_trigger_irq(cpu, VIRT_PMU_EVENT_HW_CPU_CYCLES); + pmu_timer_trigger_irq(cpu, VIRT_PMU_EVENT_HW_INSTRUCTIONS); } =20 int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr= _idx) diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 3853d0e2629e..75a22d596b69 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -30,7 +30,7 @@ void riscv_pmu_timer_cb(void *priv); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=atishp@rivosinc.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728515477447116600 Signed-off-by: Atish Patra --- target/riscv/cpu.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2ac391a7cf74..53426710f73e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -189,6 +189,28 @@ typedef struct PMUFixedCtrState { uint64_t counter_virt_prev[2]; } PMUFixedCtrState; =20 +typedef uint64_t (*PMU_EVENT_CYCLE_FUNC)(RISCVCPU *); +typedef uint64_t (*PMU_EVENT_INSTRET_FUNC)(RISCVCPU *); +typedef uint64_t (*PMU_EVENT_TLB_FUNC)(RISCVCPU *, MMUAccessType access_ty= pe); + +typedef struct PMUEventInfo { + /* Event ID (BIT [0:55] valid) */ + uint64_t event_id; + /* Supported hpmcounters for this event */ + uint32_t counter_mask; + /* Bitmask of valid event bits */ + uint64_t event_mask; +} PMUEventInfo; + +typedef struct PMUEventFunc { + /* Get the ID of the event that can monitor cycles */ + PMU_EVENT_CYCLE_FUNC get_cycle_id; + /* Get the ID of the event that can monitor cycles */ + PMU_EVENT_INSTRET_FUNC get_intstret_id; + /* Get the ID of the event that can monitor TLB events*/ + PMU_EVENT_TLB_FUNC get_tlb_access_id; +} PMUEventFunc; + struct CPUArchState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ @@ -386,6 +408,9 @@ struct CPUArchState { target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; =20 PMUFixedCtrState pmu_fixed_ctrs[2]; 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Wed, 09 Oct 2024 16:09:11 -0700 (PDT) From: Atish Patra Date: Wed, 09 Oct 2024 16:09:05 -0700 Subject: [PATCH RFC 07/10] hw/riscv/virt.c : Disassociate virt PMU events MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-pmu_event_machine-v1-7-dcbd7a60e3ba@rivosinc.com> References: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alexei.filippov@syntacore.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=atishp@rivosinc.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728515423243116600 The virt PMU related implemention should belong to virt machine file rather than common pmu.c which can be used for other implementations. Make pmu.c generic by moving all the virt PMU event related structures to it's appropriate place. Signed-off-by: Atish Patra --- hw/riscv/virt.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ target/riscv/pmu.c | 73 ++++++++++++++++++++++++++++++------------------ 2 files changed, 128 insertions(+), 26 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ee3129f3b314..ffda6d65d673 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -56,6 +56,61 @@ #include "qapi/qapi-visit-common.h" #include "hw/virtio/virtio-iommu.h" =20 +static PMUEventInfo pmu_events_arr[] =3D { + { + .event_id =3D VIRT_PMU_EVENT_HW_CPU_CYCLES, + .counter_mask =3D 0x01, + }, + { + .event_id =3D VIRT_PMU_EVENT_HW_INSTRUCTIONS, + .counter_mask =3D 0x04, + }, + { + .event_id =3D VIRT_PMU_EVENT_CACHE_DTLB_READ_MISS, + .counter_mask =3D 0, + }, + { + .event_id =3D VIRT_PMU_EVENT_CACHE_DTLB_WRITE_MISS, + .counter_mask =3D 0, + }, + { + .event_id =3D VIRT_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS, + .counter_mask =3D 0, + }, +}; + +static inline uint64_t virt_pmu_get_cycle_event_id(RISCVCPU *cpu) +{ + return VIRT_PMU_EVENT_HW_CPU_CYCLES; +} + +static inline uint64_t virt_pmu_get_instret_event_id(RISCVCPU *cpu) +{ + return VIRT_PMU_EVENT_HW_INSTRUCTIONS; +} + +static uint64_t virt_pmu_get_tlb_event_id(RISCVCPU *cpu, + MMUAccessType access_type) +{ + uint64_t tlb_event_type =3D ULONG_MAX; + + switch (access_type) { + case MMU_INST_FETCH: + tlb_event_type =3D VIRT_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; + break; + case MMU_DATA_LOAD: + tlb_event_type =3D VIRT_PMU_EVENT_CACHE_DTLB_READ_MISS; + break; + case MMU_DATA_STORE: + tlb_event_type =3D VIRT_PMU_EVENT_CACHE_DTLB_WRITE_MISS; + break; + default: + break; + } + + return tlb_event_type; +} + /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU= . */ static bool virt_use_kvm_aia(RISCVVirtState *s) { @@ -710,6 +765,29 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_phandles[socket] =3D aplic_s_phandle; } =20 +static void virt_pmu_events_init(RISCVVirtState *s) +{ + int cpu, socket, i; + MachineState *ms =3D MACHINE(s); + int num_sockets =3D riscv_socket_count(ms); + RISCVCPU *hart; + + for (socket =3D 0 ; socket < num_sockets; socket++) { + for (cpu =3D s->soc[socket].num_harts - 1; cpu >=3D 0; cpu--) { + hart =3D &s->soc[socket].harts[cpu]; + hart->env.num_pmu_events =3D 5; + /* All hpmcounters can monitor all supported events */ + for (i =3D 0; i < ARRAY_SIZE(pmu_events_arr); i++) { + pmu_events_arr[i].counter_mask |=3D hart->cfg.pmu_mask; + } + hart->env.pmu_events =3D pmu_events_arr; + hart->env.pmu_efuncs.get_cycle_id =3D virt_pmu_get_cycle_event= _id; + hart->env.pmu_efuncs.get_intstret_id =3D virt_pmu_get_instret_= event_id; + hart->env.pmu_efuncs.get_tlb_access_id =3D virt_pmu_get_tlb_ev= ent_id; + } + } +} + static void create_fdt_pmu(RISCVVirtState *s) { g_autofree char *pmu_name =3D g_strdup_printf("/pmu"); @@ -1614,6 +1692,9 @@ static void virt_machine_init(MachineState *machine) } virt_flash_map(s, system_memory); =20 + /* Setup the PMU Event details. This must happen before fdt setup */ + virt_pmu_events_init(s); + /* load/create device tree */ if (machine->dtb) { machine->fdt =3D load_device_tree(machine->dtb, &s->fdt_size); diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index c436b08d1043..3235388c66e4 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -304,7 +304,8 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum virt_pmu_eve= nt_idx event_idx) bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, uint32_t target_ctr) { - RISCVCPU *cpu; + uint64_t event_idx =3D ULONG_MAX; + RISCVCPU *cpu =3D env_archcpu(env); uint32_t ctr_idx; =20 /* Fixed instret counter */ @@ -312,9 +313,15 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState = *env, return true; } =20 - cpu =3D env_archcpu(env); - if (!riscv_pmu_htable_lookup(cpu, VIRT_PMU_EVENT_HW_INSTRUCTIONS, - &ctr_idx)) { + if (env->pmu_efuncs.get_intstret_id) { + event_idx =3D env->pmu_efuncs.get_intstret_id(cpu); + } + + if (event_idx =3D=3D ULONG_MAX) { + return false; + } + + if (!riscv_pmu_htable_lookup(cpu, event_idx, &ctr_idx)) { return false; } =20 @@ -323,7 +330,8 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *= env, =20 bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr) { - RISCVCPU *cpu; + uint64_t event_idx =3D ULONG_MAX; + RISCVCPU *cpu =3D env_archcpu(env); uint32_t ctr_idx; =20 /* Fixed mcycle counter */ @@ -331,9 +339,15 @@ bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, = uint32_t target_ctr) return true; } =20 - cpu =3D env_archcpu(env); - if (!riscv_pmu_htable_lookup(cpu, VIRT_PMU_EVENT_HW_CPU_CYCLES, - &ctr_idx)) { + if (env->pmu_efuncs.get_cycle_id) { + event_idx =3D env->pmu_efuncs.get_cycle_id(cpu); + } + + if (event_idx =3D=3D ULONG_MAX) { + return false; + } + + if (!riscv_pmu_htable_lookup(cpu, event_idx, &ctr_idx)) { return false; } =20 @@ -366,6 +380,8 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint= 64_t value, RISCVCPU *cpu =3D env_archcpu(env); uint32_t mapped_ctr_idx; gint64 *eid_ptr; + bool valid_event =3D false; + int i; =20 if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map)= { return -1; @@ -389,15 +405,14 @@ int riscv_pmu_update_event_map(CPURISCVState *env, ui= nt64_t value, return 0; } =20 - switch (event_idx) { - case VIRT_PMU_EVENT_HW_CPU_CYCLES: - case VIRT_PMU_EVENT_HW_INSTRUCTIONS: - case VIRT_PMU_EVENT_CACHE_DTLB_READ_MISS: - case VIRT_PMU_EVENT_CACHE_DTLB_WRITE_MISS: - case VIRT_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS: - break; - default: - /* We don't support any raw events right now */ + for (i =3D 0; i < env->num_pmu_events; i++) { + if (event_idx =3D=3D env->pmu_events[i].event_id) { + valid_event =3D true; + break; + } + } + + if (!valid_event) { return -1; } eid_ptr =3D g_new(gint64, 1); @@ -447,8 +462,7 @@ static bool pmu_hpmevent_set_of_if_clear(CPURISCVState = *env, uint32_t ctr_idx) return false; } =20 -static void pmu_timer_trigger_irq(RISCVCPU *cpu, - enum virt_pmu_event_idx evt_idx) +static void pmu_timer_trigger_irq(RISCVCPU *cpu, uint64_t evt_idx) { uint32_t ctr_idx; CPURISCVState *env =3D &cpu->env; @@ -457,11 +471,6 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu, uint64_t curr_ctr_val, curr_ctrh_val; uint64_t ctr_val; =20 - if (evt_idx !=3D VIRT_PMU_EVENT_HW_CPU_CYCLES && - evt_idx !=3D VIRT_PMU_EVENT_HW_INSTRUCTIONS) { - return; - } - if (!riscv_pmu_htable_lookup(cpu, evt_idx, &ctr_idx)) { return; } @@ -515,10 +524,22 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu, void riscv_pmu_timer_cb(void *priv) { RISCVCPU *cpu =3D priv; + uint64_t event_idx; + CPURISCVState *env =3D &cpu->env; =20 /* Timer event was triggered only for these events */ - pmu_timer_trigger_irq(cpu, VIRT_PMU_EVENT_HW_CPU_CYCLES); - pmu_timer_trigger_irq(cpu, VIRT_PMU_EVENT_HW_INSTRUCTIONS); + if (env->pmu_efuncs.get_cycle_id) { + event_idx =3D env->pmu_efuncs.get_cycle_id(cpu); + if (event_idx !=3D ULONG_MAX) { + pmu_timer_trigger_irq(cpu, event_idx); + } + } + if (env->pmu_efuncs.get_intstret_id) { + event_idx =3D env->pmu_efuncs.get_intstret_id(cpu); + if (event_idx !=3D ULONG_MAX) { + pmu_timer_trigger_irq(cpu, event_idx); + } + } } =20 int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr= _idx) --=20 2.34.1 From nobody Sat Nov 23 21:19:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1728515440; cv=none; d=zohomail.com; s=zohoarc; b=HhdNXKtQGxyCU9J+v+fKBkRTDWhzZ9YkniAdPlCHreaYq3YNpR9bd7qMoEIV2xz3sLmOn2RBDg6g4f7/OGjf2S3tSTAJkzJqbxiz7RsG9nmzja6iODb+Kc+cDdKtoOUWhhhrbaBO7X9J+VByoQWmt+z9xH/h1ZCqZUkhHhaioWs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1728515440; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=P6q/KHZBoxoAUwii9W1VeCsLQoaGoXXnAk+sVFIRKlQ=; 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Wed, 09 Oct 2024 16:09:12 -0700 (PDT) From: Atish Patra Date: Wed, 09 Oct 2024 16:09:06 -0700 Subject: [PATCH RFC 08/10] target/riscv: Update event mapping hashtable for invalid events MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-pmu_event_machine-v1-8-dcbd7a60e3ba@rivosinc.com> References: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alexei.filippov@syntacore.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=atishp@rivosinc.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728515441230116600 If the software programs an invalid hpmevent or selects a invalid counter mapping, the hashtable entry should be updated accordingly. Otherwise, the user may get stale value from the old mapped counter. Signed-off-by: Atish Patra --- target/riscv/pmu.c | 39 +++++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 3235388c66e4..24c2fe82c247 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -387,39 +387,42 @@ int riscv_pmu_update_event_map(CPURISCVState *env, ui= nt64_t value, return -1; } =20 - /* - * Expected mhpmevent value is zero for reset case. Remove the current - * mapping. - */ - if (!value) { - pthread_rwlock_wrlock(&cpu->pmu_map_lock); - g_hash_table_foreach_remove(cpu->pmu_event_ctr_map, - pmu_remove_event_map, - GUINT_TO_POINTER(ctr_idx)); - pthread_rwlock_unlock(&cpu->pmu_map_lock); - return 0; - } - event_idx =3D value & MHPMEVENT_IDX_MASK; if (riscv_pmu_htable_lookup(cpu, event_idx, &mapped_ctr_idx)) { return 0; } =20 for (i =3D 0; i < env->num_pmu_events; i++) { - if (event_idx =3D=3D env->pmu_events[i].event_id) { + if ((event_idx =3D=3D env->pmu_events[i].event_id) && + (BIT(ctr_idx) & env->pmu_events[i].counter_mask)) { valid_event =3D true; break; } } =20 - if (!valid_event) { - return -1; + pthread_rwlock_wrlock(&cpu->pmu_map_lock); + /* + * Remove the current mapping in the following cases: + * 1. mhpmevent value is zero which indicates a reset case. + * 2. An invalid event is programmed for mapping to a counter. + */ + if (!value || !valid_event) { + g_hash_table_foreach_remove(cpu->pmu_event_ctr_map, + pmu_remove_event_map, + GUINT_TO_POINTER(ctr_idx)); + pthread_rwlock_unlock(&cpu->pmu_map_lock); + return 0; } + eid_ptr =3D g_new(gint64, 1); *eid_ptr =3D event_idx; - pthread_rwlock_wrlock(&cpu->pmu_map_lock); + /* + * Insert operation will replace the value if the key exists + * As per the documentation, it will free the passed key is freed as w= ell. + * No special handling is required for replace or key management. + */ g_hash_table_insert(cpu->pmu_event_ctr_map, eid_ptr, - GUINT_TO_POINTER(ctr_idx)); + GUINT_TO_POINTER(ctr_idx)); pthread_rwlock_unlock(&cpu->pmu_map_lock); =20 return 0; --=20 2.34.1 From nobody Sat Nov 23 21:19:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-pmu_event_machine-v1-9-dcbd7a60e3ba@rivosinc.com> References: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alexei.filippov@syntacore.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=atishp@rivosinc.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728515375191116600 We have TLB related event call back available now. Invoke them from generic cpu helper code so that other machines can implement those as well in the future. The virt machine is the only user for now though. Signed-off-by: Atish Patra --- target/riscv/cpu_helper.c | 21 +++++++-------------- target/riscv/pmu.c | 2 +- target/riscv/pmu.h | 2 +- 3 files changed, 9 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0f1655a221bd..5161fc86dbfe 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1295,23 +1295,16 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, va= ddr addr, =20 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) { - enum virt_pmu_event_idx pmu_event_type; + uint64_t event_type =3D ULONG_MAX; + CPURISCVState *env =3D &cpu->env; =20 - switch (access_type) { - case MMU_INST_FETCH: - pmu_event_type =3D VIRT_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; - break; - case MMU_DATA_LOAD: - pmu_event_type =3D VIRT_PMU_EVENT_CACHE_DTLB_READ_MISS; - break; - case MMU_DATA_STORE: - pmu_event_type =3D VIRT_PMU_EVENT_CACHE_DTLB_WRITE_MISS; - break; - default: - return; + if (env->pmu_efuncs.get_tlb_access_id) { + event_type =3D env->pmu_efuncs.get_tlb_access_id(cpu, access_type); } =20 - riscv_pmu_incr_ctr(cpu, pmu_event_type); + if (event_type !=3D ULONG_MAX) { + riscv_pmu_incr_ctr(cpu, event_type); + } } =20 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 24c2fe82c247..e80f0f911fa3 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -274,7 +274,7 @@ void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, ta= rget_ulong newpriv, riscv_pmu_icount_update_priv(env, newpriv, new_virt); } =20 -int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum virt_pmu_event_idx event_idx) +int riscv_pmu_incr_ctr(RISCVCPU *cpu, uint64_t event_idx) { uint32_t ctr_idx; int ret; diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 75a22d596b69..810ac2fae797 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -30,7 +30,7 @@ void riscv_pmu_timer_cb(void *priv); void riscv_pmu_init(RISCVCPU *cpu, Error **errp); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); -int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum virt_pmu_event_idx event_idx); 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Wed, 09 Oct 2024 16:09:14 -0700 (PDT) From: Atish Patra Date: Wed, 09 Oct 2024 16:09:08 -0700 Subject: [PATCH RFC 10/10] hw/riscv/virt.c: Generate the PMU node from the machine MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-pmu_event_machine-v1-10-dcbd7a60e3ba@rivosinc.com> References: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alexei.filippov@syntacore.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=atishp@rivosinc.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728515417220116600 The virt machine implementation relies on the SBI PMU extension. The OpenSBI implementation requires a PMU specific DT node that is currently encodes the counter and PMU events mapping. As the PMU DT node encodes the platform specific event encodings, it should be implement in platform specific code instead of generic PMU code. Move the PMU DT node generation code from virt.c from common pmu code. Signed-off-by: Atish Patra --- hw/riscv/virt.c | 21 +++++++++++++++++++-- target/riscv/pmu.c | 36 ------------------------------------ target/riscv/pmu.h | 1 - 3 files changed, 19 insertions(+), 39 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ffda6d65d673..056afe6a6ceb 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -792,11 +792,28 @@ static void create_fdt_pmu(RISCVVirtState *s) { g_autofree char *pmu_name =3D g_strdup_printf("/pmu"); MachineState *ms =3D MACHINE(s); - RISCVCPU hart =3D s->soc[0].harts[0]; + uint32_t fdt_event_ctr_map[15] =3D {}; + int i; =20 qemu_fdt_add_subnode(ms->fdt, pmu_name); qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); - riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); + + /* + * To keep it simple, any event can be mapped to any programmable coun= ters + * in QEMU. The generic cycle & instruction count events can also be + * monitored using programmable counters. In that case, mcycle & minst= ret + * must continue to provide the correct value as well. Heterogeneous P= MU per + * hart is not supported yet. Thus, number of counters are same across= all + * harts. + */ + for (i =3D 0; i < ARRAY_SIZE(pmu_events_arr); i++) { + fdt_event_ctr_map[0 + i * 3] =3D cpu_to_be32(pmu_events_arr[i].eve= nt_id); + fdt_event_ctr_map[1 + i * 3] =3D cpu_to_be32(pmu_events_arr[i].eve= nt_id); + fdt_event_ctr_map[2 + i * 3] =3D cpu_to_be32(pmu_events_arr[i].cou= nter_mask); + } + /* This a OpenSBI specific DT property documented in OpenSBI docs */ + qemu_fdt_setprop(ms->fdt, pmu_name, "riscv,event-to-mhpmcounters", + fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); } =20 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memma= p, diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index e80f0f911fa3..dd0a18ae3dc1 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -27,42 +27,6 @@ =20 #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ =20 -/* - * To keep it simple, any event can be mapped to any programmable counters= in - * QEMU. The generic cycle & instruction count events can also be monitored - * using programmable counters. In that case, mcycle & minstret must conti= nue - * to provide the correct value as well. Heterogeneous PMU per hart is not - * supported yet. Thus, number of counters are same across all harts. - */ -void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name) -{ - uint32_t fdt_event_ctr_map[15] =3D {}; - - fdt_event_ctr_map[0] =3D cpu_to_be32(VIRT_PMU_EVENT_HW_CPU_CYCLES); - fdt_event_ctr_map[1] =3D cpu_to_be32(VIRT_PMU_EVENT_HW_CPU_CYCLES); - fdt_event_ctr_map[2] =3D cpu_to_be32(cmask | 1 << 0); - - fdt_event_ctr_map[3] =3D cpu_to_be32(VIRT_PMU_EVENT_HW_INSTRUCTIONS); - fdt_event_ctr_map[4] =3D cpu_to_be32(VIRT_PMU_EVENT_HW_INSTRUCTIONS); - fdt_event_ctr_map[5] =3D cpu_to_be32(cmask | 1 << 2); - - fdt_event_ctr_map[6] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_DTLB_READ_MIS= S); - fdt_event_ctr_map[7] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_DTLB_READ_MIS= S); - fdt_event_ctr_map[8] =3D cpu_to_be32(cmask); - - fdt_event_ctr_map[9] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_DTLB_WRITE_MI= SS); - fdt_event_ctr_map[10] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_DTLB_WRITE_M= ISS); - fdt_event_ctr_map[11] =3D cpu_to_be32(cmask); - - fdt_event_ctr_map[12] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_ITLB_PREFETC= H_MISS); - fdt_event_ctr_map[13] =3D cpu_to_be32(VIRT_PMU_EVENT_CACHE_ITLB_PREFETC= H_MISS); - fdt_event_ctr_map[14] =3D cpu_to_be32(cmask); - - /* This a OpenSBI specific DT property documented in OpenSBI docs */ - qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters", - fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); -} - static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) { if (ctr_idx < 3 || ctr_idx >=3D RV_MAX_MHPMCOUNTERS || diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 810ac2fae797..10505040d9e5 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -31,7 +31,6 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); int riscv_pmu_incr_ctr(RISCVCPU *cpu, uint64_t event_idx); -void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name= ); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, --=20 2.34.1