From nobody Thu Nov 14 16:32:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1728427955; cv=none; d=zohomail.com; s=zohoarc; b=Y7QGv743XMY6r4vCf7LAcUBn8fk+l/Mwg8XOGn24rCLkAi6oujm++xMybtD9cfPwBOJr/hmInbMXpX6CD0XvARKoavwhvIki9rDP1CylmcMi9tbf9gxeZ5AQ5ypZj2SDHY8Y9pS6UKOEPzFeby0JpcwlMEQF/U3sOdGtz5puXFQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1728427955; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rSoL3SXlNF/tYJc6qw9RykMfpe2L0Nqr6O9wZWAdkWA=; b=NKwSMp9odLgGG1PlZZjT/f3No6OB0je7PogeIEZDdxuJI+w6UtsfL7cKLh1wswEg+cFNi/wAyoiXzLqOreIQzwITE3IDWRDJ0XefHBU6cgwZA70uNgeKmRd+QfApSEFWdEzHJdd83CQI7/ZyKDQKCVQibEpGf4mAUG4nhpKnyDk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1728427955772789.3523054145855; Tue, 8 Oct 2024 15:52:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1syJ2b-0000Vg-85; Tue, 08 Oct 2024 18:50:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1syJ2X-0000RT-Do for qemu-devel@nongnu.org; Tue, 08 Oct 2024 18:50:49 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1syJ2Q-0003zf-6j for qemu-devel@nongnu.org; Tue, 08 Oct 2024 18:50:49 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-20bc2970df5so46901435ad.3 for ; Tue, 08 Oct 2024 15:50:34 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138af962sm60006105ad.26.2024.10.08.15.50.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 15:50:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1728427833; x=1729032633; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rSoL3SXlNF/tYJc6qw9RykMfpe2L0Nqr6O9wZWAdkWA=; b=BHkeh2A1IA5Y9+gDTuU4VkJ8RMINP5PoG04tFksg7kjDd7TiJG56FORbkWdL/FylL3 1JCfz0s42Wb6DRellSTuk4QsNf5iWpjQUYUih33CgkdioFeKZnqeQ7xllbrxfSDKyDBK NpLkXrGgR9CBGBC44nd5FTFUyis1QeWUzvDnP0AWXwOjDM082h/bS0le3gSDJzJUeWWR BNYNcsSkDxaOO+e0XycoiA44z0UMp6yeDAryqUeNrRP/mgAORE6O8/8ErhLnwwyqN5vV wkZYnsQ0ol5Nk6oRQExf2QI05t7oYcCCeBIy75vrqQfANRqyoKmoP+NeZl8zHCwwIU8e cANw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728427833; x=1729032633; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rSoL3SXlNF/tYJc6qw9RykMfpe2L0Nqr6O9wZWAdkWA=; b=dv1tz3LHgm770vx7dLFYLesksDuUEt6I1Hmw95wajD4lO1JpvrYvFIsfY6n5ls5DA6 heD5ZMqDXtbZ2h2jQHPT9/kJxuz3oI0gFiOd+/CaHnGeQsSB6LWA3fVAODFrSPJnuvho 7VkPZXUamcR5oI1owHc/enPmScD6OKCDz4fo7lJqSreYTIbgKM5QjCb3lPrsgSbf1qmh u77BOofQAynHKEu7+ND5wBLLJSYK9Q1wknwha+sDaE94dnzIRZz7CuRV0e1/5iAgq50g SxTWy0jg9HDqnJigauuaZSvTn/aN6UmO2qDgtEd08Da+dRSeI29narkxZGh+BHgA1JDz wdwg== X-Forwarded-Encrypted: i=1; AJvYcCUiIS4+TFTBzOyvuOASRYo4xshMatfCmqHIpPvQjgDU9pq9spzNU4jzy3AvDJBDpYVuyFSVozOz1ZPB@nongnu.org X-Gm-Message-State: AOJu0Yz/fE8AP/KxuF/Pu9YFCJ1KZz/jJOv0f2YGDiFTGEKxrSgXPaRZ JH3QryBqVqzrQ+UqlaW5WfKU5E+9fSwkJGlx8+NyluG9qvux2cLiL4rY5ZU8HO4= X-Google-Smtp-Source: AGHT+IH/+msPb1oowCNMzuLRKcUq5BRtZgXPHX/A/yKqe7y1nQkO88q2zo0Ig6THfWYIVvoL1EHttQ== X-Received: by 2002:a17:902:ec82:b0:20b:b794:b39f with SMTP id d9443c01a7336-20c637866e1mr6999955ad.30.1728427833528; Tue, 08 Oct 2024 15:50:33 -0700 (PDT) From: Deepak Gupta To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com, kito.cheng@sifive.com, Deepak Gupta , Richard Henderson , Alistair Francis Subject: [PATCH v16 15/20] target/riscv: update `decode_save_opc` to store extra word2 Date: Tue, 8 Oct 2024 15:50:05 -0700 Message-ID: <20241008225010.1861630-16-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241008225010.1861630-1-debug@rivosinc.com> References: <20241008225010.1861630-1-debug@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=debug@rivosinc.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728427956431116600 Content-Type: text/plain; charset="utf-8" Extra word 2 is stored during tcg compile and `decode_save_opc` needs additional argument in order to pass the value. This will be used during unwind to get extra information about instruction like how to massage exceptions. Updated all callsites as well. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/594 Signed-off-by: Deepak Gupta Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_privileged.c.inc | 8 ++++---- target/riscv/insn_trans/trans_rva.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvd.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvf.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvh.c.inc | 8 ++++---- target/riscv/insn_trans/trans_rvi.c.inc | 6 +++--- target/riscv/insn_trans/trans_rvvk.c.inc | 10 +++++----- target/riscv/insn_trans/trans_rvzacas.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvzfh.c.inc | 4 ++-- target/riscv/insn_trans/trans_svinval.c.inc | 6 +++--- target/riscv/translate.c | 11 ++++++----- 11 files changed, 35 insertions(+), 34 deletions(-) diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index bc5263a4e0..ecd3b8b2c9 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -78,7 +78,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) { #ifndef CONFIG_USER_ONLY if (has_ext(ctx, RVS)) { - decode_save_opc(ctx); + decode_save_opc(ctx, 0); translator_io_start(&ctx->base); gen_helper_sret(cpu_pc, tcg_env); exit_tb(ctx); /* no chaining */ @@ -95,7 +95,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY - decode_save_opc(ctx); + decode_save_opc(ctx, 0); translator_io_start(&ctx->base); gen_helper_mret(cpu_pc, tcg_env); exit_tb(ctx); /* no chaining */ @@ -109,7 +109,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) static bool trans_wfi(DisasContext *ctx, arg_wfi *a) { #ifndef CONFIG_USER_ONLY - decode_save_opc(ctx); + decode_save_opc(ctx, 0); gen_update_pc(ctx, ctx->cur_insn_len); gen_helper_wfi(tcg_env); return true; @@ -121,7 +121,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a) static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a) { #ifndef CONFIG_USER_ONLY - decode_save_opc(ctx); + decode_save_opc(ctx, 0); gen_helper_tlb_flush(tcg_env); return true; #endif diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index 39bbf60f3c..9cf3ae8019 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -34,7 +34,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemO= p mop) { TCGv src1; =20 - decode_save_opc(ctx); + decode_save_opc(ctx, 0); src1 =3D get_address(ctx, a->rs1, 0); if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); @@ -61,7 +61,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemO= p mop) TCGLabel *l1 =3D gen_new_label(); TCGLabel *l2 =3D gen_new_label(); =20 - decode_save_opc(ctx); + decode_save_opc(ctx, 0); src1 =3D get_address(ctx, a->rs1, 0); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); =20 diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 8a46124f98..30883ea37c 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -61,7 +61,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) memop |=3D MO_ATOM_IFALIGN; } =20 - decode_save_opc(ctx); + decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, memop); =20 @@ -85,7 +85,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) memop |=3D MO_ATOM_IFALIGN; } =20 - decode_save_opc(ctx); + decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, memop); return true; diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index 0222a728df..ed73afe089 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -52,7 +52,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) memop |=3D MO_ATOM_WITHIN16; } =20 - decode_save_opc(ctx); + decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); dest =3D cpu_fpr[a->rd]; tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, memop); @@ -74,7 +74,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) memop |=3D MO_ATOM_WITHIN16; } =20 - decode_save_opc(ctx); + decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, memop); return true; diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index aa9d41c18c..03c6694430 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -44,7 +44,7 @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a, TCGv dest =3D dest_gpr(ctx, a->rd); TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); =20 - decode_save_opc(ctx); + decode_save_opc(ctx, 0); func(dest, tcg_env, addr); gen_set_gpr(ctx, a->rd, dest); return true; @@ -56,7 +56,7 @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a, TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 - decode_save_opc(ctx); + decode_save_opc(ctx, 0); func(tcg_env, addr, data); return true; } @@ -147,7 +147,7 @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sf= ence_vma *a) { REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY - decode_save_opc(ctx); + decode_save_opc(ctx, 0); gen_helper_hyp_gvma_tlb_flush(tcg_env); return true; #endif @@ -158,7 +158,7 @@ static bool trans_hfence_vvma(DisasContext *ctx, arg_sf= ence_vma *a) { REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY - decode_save_opc(ctx); + decode_save_opc(ctx, 0); gen_helper_hyp_tlb_flush(tcg_env); return true; #endif diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 638fc0fb7b..96c218a9d7 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -326,7 +326,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemO= p memop) if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } - decode_save_opc(ctx); + decode_save_opc(ctx, 0); if (get_xl(ctx) =3D=3D MXL_RV128) { out =3D gen_load_i128(ctx, a, memop); } else { @@ -427,7 +427,7 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, Mem= Op memop) if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } - decode_save_opc(ctx); + decode_save_opc(ctx, 0); if (get_xl(ctx) =3D=3D MXL_RV128) { return gen_store_i128(ctx, a, memop); } else { @@ -889,7 +889,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_= i *a) static bool do_csr_post(DisasContext *ctx) { /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ - decode_save_opc(ctx); + decode_save_opc(ctx, 0); /* We may have changed important cpu state -- exit to main loop. */ gen_update_pc(ctx, ctx->cur_insn_len); exit_tb(ctx); diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index ae1f40174a..27bf3f0b68 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -249,7 +249,7 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll= _vx_check) = \ if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { = \ /* save opcode for unwinding in case we throw an exception= */ \ - decode_save_opc(s); = \ + decode_save_opc(s, 0); = \ egs =3D tcg_constant_i32(EGS); = \ gen_helper_egs_check(egs, tcg_env); = \ } = \ @@ -322,7 +322,7 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_E= GS) = \ if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { = \ /* save opcode for unwinding in case we throw an exception= */ \ - decode_save_opc(s); = \ + decode_save_opc(s, 0); = \ egs =3D tcg_constant_i32(EGS); = \ gen_helper_egs_check(egs, tcg_env); = \ } = \ @@ -389,7 +389,7 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED= _EGS) = \ if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { = \ /* save opcode for unwinding in case we throw an exception= */ \ - decode_save_opc(s); = \ + decode_save_opc(s, 0); = \ egs =3D tcg_constant_i32(EGS); = \ gen_helper_egs_check(egs, tcg_env); = \ } = \ @@ -440,7 +440,7 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr = *a) =20 if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { /* save opcode for unwinding in case we throw an exception */ - decode_save_opc(s); + decode_save_opc(s, 0); egs =3D tcg_constant_i32(ZVKNH_EGS); gen_helper_egs_check(egs, tcg_env); } @@ -471,7 +471,7 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr = *a) =20 if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { /* save opcode for unwinding in case we throw an exception */ - decode_save_opc(s); + decode_save_opc(s, 0); egs =3D tcg_constant_i32(ZVKNH_EGS); gen_helper_egs_check(egs, tcg_env); } diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/ins= n_trans/trans_rvzacas.c.inc index fcced99fc7..15e688a033 100644 --- a/target/riscv/insn_trans/trans_rvzacas.c.inc +++ b/target/riscv/insn_trans/trans_rvzacas.c.inc @@ -76,7 +76,7 @@ static bool gen_cmpxchg64(DisasContext *ctx, arg_atomic *= a, MemOp mop) TCGv src1 =3D get_address(ctx, a->rs1, 0); TCGv_i64 src2 =3D get_gpr_pair(ctx, a->rs2); =20 - decode_save_opc(ctx); + decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); tcg_gen_atomic_cmpxchg_i64(dest, src1, dest, src2, ctx->mem_idx, mop); =20 gen_set_gpr_pair(ctx, a->rd, dest); @@ -121,7 +121,7 @@ static bool trans_amocas_q(DisasContext *ctx, arg_amoca= s_q *a) =20 tcg_gen_concat_i64_i128(src2, src2l, src2h); tcg_gen_concat_i64_i128(dest, destl, desth); - decode_save_opc(ctx); + decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); tcg_gen_atomic_cmpxchg_i128(dest, src1, dest, src2, ctx->mem_idx, (MO_ALIGN | MO_TEUO)); =20 diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_= trans/trans_rvzfh.c.inc index 1eb458b491..bece48e600 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -48,7 +48,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) REQUIRE_FPU; REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); =20 - decode_save_opc(ctx); + decode_save_opc(ctx, 0); t0 =3D get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { TCGv temp =3D tcg_temp_new(); @@ -71,7 +71,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) REQUIRE_FPU; REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); =20 - decode_save_opc(ctx); + decode_save_opc(ctx, 0); t0 =3D get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { TCGv temp =3D tcg_temp_new(); diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/ins= n_trans/trans_svinval.c.inc index 0f692a1088..a06c3b214f 100644 --- a/target/riscv/insn_trans/trans_svinval.c.inc +++ b/target/riscv/insn_trans/trans_svinval.c.inc @@ -28,7 +28,7 @@ static bool trans_sinval_vma(DisasContext *ctx, arg_sinva= l_vma *a) /* Do the same as sfence.vma currently */ REQUIRE_EXT(ctx, RVS); #ifndef CONFIG_USER_ONLY - decode_save_opc(ctx); + decode_save_opc(ctx, 0); gen_helper_tlb_flush(tcg_env); return true; #endif @@ -57,7 +57,7 @@ static bool trans_hinval_vvma(DisasContext *ctx, arg_hinv= al_vvma *a) /* Do the same as hfence.vvma currently */ REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY - decode_save_opc(ctx); + decode_save_opc(ctx, 0); gen_helper_hyp_tlb_flush(tcg_env); return true; #endif @@ -70,7 +70,7 @@ static bool trans_hinval_gvma(DisasContext *ctx, arg_hinv= al_gvma *a) /* Do the same as hfence.gvma currently */ REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY - decode_save_opc(ctx); + decode_save_opc(ctx, 0); gen_helper_hyp_gvma_tlb_flush(tcg_env); return true; #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0322597bf6..0ca10818f3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -209,11 +209,12 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64= in) tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); } =20 -static void decode_save_opc(DisasContext *ctx) +static void decode_save_opc(DisasContext *ctx, target_ulong excp_uw2) { assert(!ctx->insn_start_updated); ctx->insn_start_updated =3D true; tcg_set_insn_start_param(ctx->base.insn_start, 1, ctx->opcode); + tcg_set_insn_start_param(ctx->base.insn_start, 2, excp_uw2); } =20 static void gen_pc_plus_diff(TCGv target, DisasContext *ctx, @@ -699,7 +700,7 @@ static void gen_set_rm(DisasContext *ctx, int rm) } =20 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ - decode_save_opc(ctx); + decode_save_opc(ctx, 0); gen_helper_set_rounding_mode(tcg_env, tcg_constant_i32(rm)); } =20 @@ -712,7 +713,7 @@ static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) ctx->frm_valid =3D true; =20 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ - decode_save_opc(ctx); + decode_save_opc(ctx, 0); gen_helper_set_rounding_mode_chkfrm(tcg_env, tcg_constant_i32(rm)); } =20 @@ -1096,7 +1097,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, mop |=3D MO_ALIGN; } =20 - decode_save_opc(ctx); + decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); src1 =3D get_address(ctx, a->rs1, 0); func(dest, src1, src2, ctx->mem_idx, mop); =20 @@ -1110,7 +1111,7 @@ static bool gen_cmpxchg(DisasContext *ctx, arg_atomic= *a, MemOp mop) TCGv src1 =3D get_address(ctx, a->rs1, 0); TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 - decode_save_opc(ctx); + decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop); =20 gen_set_gpr(ctx, a->rd, dest); --=20 2.45.0