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Tue, 08 Oct 2024 15:50:32 -0700 (PDT) From: Deepak Gupta To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com, kito.cheng@sifive.com, Deepak Gupta , Richard Henderson , Alistair Francis Subject: [PATCH v16 14/20] target/riscv: AMO operations always raise store/AMO fault Date: Tue, 8 Oct 2024 15:50:04 -0700 Message-ID: <20241008225010.1861630-15-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241008225010.1861630-1-debug@rivosinc.com> References: <20241008225010.1861630-1-debug@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=debug@rivosinc.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728428088939116600 Content-Type: text/plain; charset="utf-8" This patch adds one more word for tcg compile which can be obtained during unwind time to determine fault type for original operation (example AMO). Depending on that, fault can be promoted to store/AMO fault. Signed-off-by: Deepak Gupta Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 9 ++++++++- target/riscv/cpu_helper.c | 20 ++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 1 + target/riscv/translate.c | 2 +- 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d39650636c..fb93b0c859 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -46,8 +46,13 @@ typedef struct CPUArchState CPURISCVState; /* * RISC-V-specific extra insn start words: * 1: Original instruction opcode + * 2: more information about instruction */ -#define TARGET_INSN_START_EXTRA_WORDS 1 +#define TARGET_INSN_START_EXTRA_WORDS 2 +/* + * b0: Whether a instruction always raise a store AMO or not. + */ +#define RISCV_UW2_ALWAYS_STORE_AMO 1 =20 #define RV(x) ((target_ulong)1 << (x - 'A')) =20 @@ -234,6 +239,8 @@ struct CPUArchState { bool elp; /* shadow stack register for zicfiss extension */ target_ulong ssp; + /* env place holder for extra word 2 during unwind */ + target_ulong excp_uw2; /* sw check code for sw check exception */ target_ulong sw_check_code; #ifdef CONFIG_USER_ONLY diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8f7871c92b..201f7bf09e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1757,6 +1757,22 @@ static target_ulong riscv_transformed_insn(CPURISCVS= tate *env, return xinsn; } =20 +static target_ulong promote_load_fault(target_ulong orig_cause) +{ + switch (orig_cause) { + case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: + return RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; + + case RISCV_EXCP_LOAD_ACCESS_FAULT: + return RISCV_EXCP_STORE_AMO_ACCESS_FAULT; + + case RISCV_EXCP_LOAD_PAGE_FAULT: + return RISCV_EXCP_STORE_PAGE_FAULT; + } + + /* if no promotion, return original cause */ + return orig_cause; +} /* * Handle Traps * @@ -1769,6 +1785,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) CPURISCVState *env =3D &cpu->env; bool virt =3D env->virt_enabled; bool write_gva =3D false; + bool always_storeamo =3D (env->excp_uw2 & RISCV_UW2_ALWAYS_STORE_AMO); uint64_t s; =20 /* @@ -1804,6 +1821,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: + if (always_storeamo) { + cause =3D promote_load_fault(cause); + } write_gva =3D env->two_stage_lookup; tval =3D env->badaddr; if (env->two_stage_indirect_lookup) { diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 6c0c319499..c62c221696 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -129,6 +129,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, env->pc =3D pc; } env->bins =3D data[1]; + env->excp_uw2 =3D data[2]; } =20 static const TCGCPUOps riscv_tcg_ops =3D { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index afa2ed4e3a..0322597bf6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1264,7 +1264,7 @@ static void riscv_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) pc_next &=3D ~TARGET_PAGE_MASK; } =20 - tcg_gen_insn_start(pc_next, 0); + tcg_gen_insn_start(pc_next, 0, 0); ctx->insn_start_updated =3D false; } =20 --=20 2.45.0