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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1728374298; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jLdx1/Cl7gGjeFgtGWbyh6ai0MP7WgSk3tPWW14XjmA=; b=U5TpheTs6cgOpnMg9HnA/Yi8F4awiIFGvGWB53bcTIYd92I3KP4t7Gl94ZLUOhpPz73+JQ RqD/N0N1mtlNVhgo0DO1Bgt24ve7JJol47BBnEbOzLm0iAyHxCzo3H1RzV80TBPw+l0N5O E5isW15ikUdYdOOvO1ljooFgFut/t34= X-MC-Unique: bvFbGr2UME6tXyJYYE3ZYg-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org, berrange@redhat.com Cc: kris.conklin@seagate.com, jonathan.henze@seagate.com, evan.burgess@seagate.com, peter.maydell@linaro.org, Alejandro Zeise , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v5 16/16] hw/misc/aspeed_hace: Fix SG Accumulative hashing Date: Tue, 8 Oct 2024 09:57:23 +0200 Message-ID: <20241008075724.2772149-17-clg@redhat.com> In-Reply-To: <20241008075724.2772149-1-clg@redhat.com> References: <20241008075724.2772149-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.153, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1728374498626116600 From: Alejandro Zeise Make the Aspeed HACE module use the new qcrypto accumulative hashing functi= ons when in scatter-gather accumulative mode. A hash context will maintain a "running-hash" as each scatter-gather chunk is received. Previously each scatter-gather "chunk" was cached so the hash could be computed once the final chunk was received. However, the cache was a shallow copy, so once the guest overwrote the memory provided to HACE the final hash would not be correct. Possibly related to: https://gitlab.com/qemu-project/qemu/-/issues/1121 Buglink: https://github.com/openbmc/qemu/issues/36 Signed-off-by: Alejandro Zeise [ clg: - Checkpatch fixes ] Signed-off-by: C=C3=A9dric Le Goater --- include/hw/misc/aspeed_hace.h | 4 ++ hw/misc/aspeed_hace.c | 96 +++++++++++++++++++---------------- 2 files changed, 56 insertions(+), 44 deletions(-) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index ecb1b67de816..4af99191955a 100644 --- a/include/hw/misc/aspeed_hace.h +++ b/include/hw/misc/aspeed_hace.h @@ -1,6 +1,7 @@ /* * ASPEED Hash and Crypto Engine * + * Copyright (c) 2024 Seagate Technology LLC and/or its Affiliates * Copyright (C) 2021 IBM Corp. * * SPDX-License-Identifier: GPL-2.0-or-later @@ -10,6 +11,7 @@ #define ASPEED_HACE_H =20 #include "hw/sysbus.h" +#include "crypto/hash.h" =20 #define TYPE_ASPEED_HACE "aspeed.hace" #define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400" @@ -35,6 +37,8 @@ struct AspeedHACEState { =20 MemoryRegion *dram_mr; AddressSpace dram_as; + + QCryptoHash *hash_ctx; }; =20 =20 diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index b6f43f65b29a..8c88a1dc1ca0 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -1,6 +1,7 @@ /* * ASPEED Hash and Crypto Engine * + * Copyright (c) 2024 Seagate Technology LLC and/or its Affiliates * Copyright (C) 2021 IBM Corp. * * Joel Stanley @@ -151,50 +152,28 @@ static int reconstruct_iov(AspeedHACEState *s, struct= iovec *iov, int id, return iov_count; } =20 -/** - * Generate iov for accumulative mode. - * - * @param s aspeed hace state object - * @param iov iov of the current request - * @param id index of the current iov - * @param req_len length of the current request - * - * @return count of iov - */ -static int gen_acc_mode_iov(AspeedHACEState *s, struct iovec *iov, int id, - hwaddr *req_len) -{ - uint32_t pad_offset; - uint32_t total_msg_len; - s->total_req_len +=3D *req_len; - - if (has_padding(s, &iov[id], *req_len, &total_msg_len, &pad_offset)) { - if (s->iov_count) { - return reconstruct_iov(s, iov, id, &pad_offset); - } - - *req_len -=3D s->total_req_len - total_msg_len; - s->total_req_len =3D 0; - iov[id].iov_len =3D *req_len; - } else { - s->iov_cache[s->iov_count].iov_base =3D iov->iov_base; - s->iov_cache[s->iov_count].iov_len =3D *req_len; - ++s->iov_count; - } - - return id + 1; -} - static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, bool acc_mode) { struct iovec iov[ASPEED_HACE_MAX_SG]; + uint32_t total_msg_len; + uint32_t pad_offset; g_autofree uint8_t *digest_buf =3D NULL; size_t digest_len =3D 0; - int niov =3D 0; + bool sg_acc_mode_final_request =3D false; int i; void *haddr; =20 + if (acc_mode && s->hash_ctx =3D=3D NULL) { + s->hash_ctx =3D qcrypto_hash_new(algo, NULL); + if (s->hash_ctx =3D=3D NULL) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: qcrypto failed to create hash context\n", + __func__); + return; + } + } + if (sg_mode) { uint32_t len =3D 0; =20 @@ -226,8 +205,16 @@ static void do_hash_operation(AspeedHACEState *s, int = algo, bool sg_mode, } iov[i].iov_base =3D haddr; if (acc_mode) { - niov =3D gen_acc_mode_iov(s, iov, i, &plen); - + s->total_req_len +=3D plen; + + if (has_padding(s, &iov[i], plen, &total_msg_len, + &pad_offset)) { + /* Padding being present indicates the final request */ + sg_acc_mode_final_request =3D true; + iov[i].iov_len =3D pad_offset; + } else { + iov[i].iov_len =3D plen; + } } else { iov[i].iov_len =3D plen; } @@ -252,20 +239,36 @@ static void do_hash_operation(AspeedHACEState *s, int= algo, bool sg_mode, * required to check whether cache is empty. If no, we should * combine cached iov and the current iov. */ - uint32_t total_msg_len; - uint32_t pad_offset; s->total_req_len +=3D len; if (has_padding(s, iov, len, &total_msg_len, &pad_offset)) { - niov =3D reconstruct_iov(s, iov, 0, &pad_offset); + i =3D reconstruct_iov(s, iov, 0, &pad_offset); } } } =20 - if (niov) { - i =3D niov; - } + if (acc_mode) { + if (qcrypto_hash_updatev(s->hash_ctx, iov, i, NULL) < 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: qcrypto hash update failed\n", __func__); + return; + } + + if (sg_acc_mode_final_request) { + if (qcrypto_hash_finalize_bytes(s->hash_ctx, &digest_buf, + &digest_len, NULL)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: qcrypto failed to finalize hash\n", + __func__); + } =20 - if (qcrypto_hash_bytesv(algo, iov, i, &digest_buf, &digest_len, NULL) = < 0) { + qcrypto_hash_free(s->hash_ctx); + + s->hash_ctx =3D NULL; + s->iov_count =3D 0; + s->total_req_len =3D 0; + } + } else if (qcrypto_hash_bytesv(algo, iov, i, &digest_buf, + &digest_len, NULL) < 0) { qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); return; } @@ -397,6 +400,11 @@ static void aspeed_hace_reset(DeviceState *dev) { struct AspeedHACEState *s =3D ASPEED_HACE(dev); =20 + if (s->hash_ctx !=3D NULL) { + qcrypto_hash_free(s->hash_ctx); + s->hash_ctx =3D NULL; + } + memset(s->regs, 0, sizeof(s->regs)); s->iov_count =3D 0; s->total_req_len =3D 0; --=20 2.46.2