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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::44a; envelope-from=3q4gEZwUKCg47o9w3u22uzs.q204s08-rs9sz121u18.25u@flex--tavip.bounces.google.com; helo=mail-pf1-x44a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.024, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1728350684728116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add test to exercise clocks set and clear, system PLL initialization, audio PLL initialization, systick and ostimer clock source selection. Signed-off-by: Octavian Purdila --- tests/qtest/rt500-clkctl-test.c | 195 ++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 196 insertions(+) create mode 100644 tests/qtest/rt500-clkctl-test.c diff --git a/tests/qtest/rt500-clkctl-test.c b/tests/qtest/rt500-clkctl-tes= t.c new file mode 100644 index 0000000000..d5b83d81da --- /dev/null +++ b/tests/qtest/rt500-clkctl-test.c @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2024 Google LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/main-loop.h" +#include "exec/memory.h" +#include "hw/clock.h" +#include "hw/irq.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" + +#include "hw/misc/rt500_clkctl0.h" +#include "hw/misc/rt500_clkctl1.h" +#include "hw/misc/rt500_clk_freqs.h" +#include "hw/arm/svd/rt500.h" +#include "reg-utils.h" + +#define SYSCLK_HZ 200000000 +#define CLKCTL0_NAME "/machine/soc/clkctl0" +#define CLKCTL1_NAME "/machine/soc/clkctl1" + +static void pscctl_test(gconstpointer user_data) +{ + /* rom controller clock should be enabled at reset */ + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, PSCCTL0, ROM_CTRLR_CLK) =3D= =3D 1); + + /* DSP clk is disabled at reset */ + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, PSCCTL0, DSP_CLK) =3D=3D 0); + + /* check PSCTL_SET functionality */ + REG32_WRITE_FIELD_NOUPDATE(RT500_CLKCTL0, PSCCTL0_SET, DSP_CLK, 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, PSCCTL0, DSP_CLK) =3D=3D 1); + + /* check PSCTL_CLR functionality */ + REG32_WRITE_FIELD_NOUPDATE(RT500_CLKCTL0, PSCCTL0_CLR, DSP_CLK, 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, PSCCTL0, DSP_CLK) =3D=3D 0); + + /* FLEXIO clk is disabled at reset */ + g_assert(REG32_READ_FIELD(RT500_CLKCTL1, PSCCTL0, FlexIO) =3D=3D 0); + + /* check PSCTL_SET functionality */ + REG32_WRITE_FIELD_NOUPDATE(RT500_CLKCTL1, PSCCTL0_SET, FlexIO, 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL1, PSCCTL0, FlexIO) =3D=3D 1); + + /* check PSCTL_CLR functionality */ + REG32_WRITE_FIELD_NOUPDATE(RT500_CLKCTL1, PSCCTL0_CLR, FlexIO, 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL1, PSCCTL0, FlexIO) =3D=3D 0); +} + +static void audiopll0pfd_test(gconstpointer user_data) +{ + /* audio plls are gated at boot */ + g_assert(REG32_READ_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD3_CLKGATE) = =3D=3D 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD2_CLKGATE) = =3D=3D 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD1_CLKGATE) = =3D=3D 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD0_CLKGATE) = =3D=3D 1); + + /* ,,, and clocks are not ready */ + g_assert(REG32_READ_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD3_CLKRDY) = =3D=3D 0); + g_assert(REG32_READ_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD2_CLKRDY) = =3D=3D 0); + g_assert(REG32_READ_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD1_CLKRDY) = =3D=3D 0); + g_assert(REG32_READ_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD0_CLKRDY) = =3D=3D 0); + + /* ungate all plls and check that clocks are ready */ + REG32_WRITE_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD3_CLKGATE, 0); + REG32_WRITE_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD2_CLKGATE, 0); + REG32_WRITE_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD1_CLKGATE, 0); + REG32_WRITE_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD0_CLKGATE, 0); + + g_assert(REG32_READ_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD3_CLKRDY) = =3D=3D 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD2_CLKRDY) = =3D=3D 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD1_CLKRDY) = =3D=3D 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL1, AUDIOPLL0PFD, PFD0_CLKRDY) = =3D=3D 1); +} + +static void syspll0pfd_test(gconstpointer user_data) +{ + /* system plls are gated at boot */ + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD3_CLKGATE) =3D= =3D 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD2_CLKGATE) =3D= =3D 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD1_CLKGATE) =3D= =3D 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD0_CLKGATE) =3D= =3D 1); + + /* ,,, and clocks are not ready */ + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD3_CLKRDY) =3D= =3D 0); + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD2_CLKRDY) =3D= =3D 0); + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD1_CLKRDY) =3D= =3D 0); + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD0_CLKRDY) =3D= =3D 0); + + /* ungate all plls and check that clocks are ready */ + REG32_WRITE_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD3_CLKGATE, 0); + REG32_WRITE_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD2_CLKGATE, 0); + REG32_WRITE_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD1_CLKGATE, 0); + REG32_WRITE_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD0_CLKGATE, 0); + + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD3_CLKRDY) =3D= =3D 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD2_CLKRDY) =3D= =3D 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD1_CLKRDY) =3D= =3D 1); + g_assert(REG32_READ_FIELD(RT500_CLKCTL0, SYSPLL0PFD, PFD0_CLKRDY) =3D= =3D 1); +} + +static void systick_clk_test(gconstpointer user_data) +{ + /* systick is not running at reset */ + g_assert_cmpuint(dev_clock_out_get_hz(CLKCTL0_NAME, "systick_clk"), = =3D=3D, 0); + + /* select divout no divisor */ + REG32_WRITE_FIELD(RT500_CLKCTL0, SYSTICKFCLKSEL, SEL, + SYSTICKFCLKSEL_DIVOUT); + g_assert_cmpuint(dev_clock_out_get_hz(CLKCTL0_NAME, "systick_clk"), + =3D=3D, SYSCLK_HZ); + + /* change divisor to 2 */ + REG32_WRITE_FIELD(RT500_CLKCTL0, SYSTICKFCLKDIV, DIV, 1); + g_assert_cmpuint(dev_clock_out_get_hz(CLKCTL0_NAME, "systick_clk"), + =3D=3D, SYSCLK_HZ / 2); + + /* select lpsoc */ + REG32_WRITE_FIELD(RT500_CLKCTL0, SYSTICKFCLKSEL, SEL, + SYSTICKFCLKSEL_LPOSC); + g_assert_cmpuint(dev_clock_out_get_hz(CLKCTL0_NAME, "systick_clk"), + =3D=3D, LPOSC_CLK_HZ); + + /* select lpsoc */ + REG32_WRITE_FIELD(RT500_CLKCTL0, SYSTICKFCLKSEL, SEL, + SYSTICKFCLKSEL_32KHZRTC); + g_assert_cmpuint(dev_clock_out_get_hz(CLKCTL0_NAME, "systick_clk"), + =3D=3D, RTC32KHZ_CLK_HZ); + + /* disable clock */ + REG32_WRITE_FIELD(RT500_CLKCTL0, SYSTICKFCLKSEL, SEL, + SYSTICKFCLKSEL_NONE); + g_assert_cmpuint(dev_clock_out_get_hz(CLKCTL0_NAME, "systick_clk"), + =3D=3D, 0); +} + +static void ostimer_clk_test(gconstpointer user_data) +{ + /* systick is not running at reset */ + g_assert_cmpuint(dev_clock_out_get_hz(CLKCTL1_NAME, "ostimer_clk"), = =3D=3D, 0); + + /* select lpsoc */ + REG32_WRITE_FIELD(RT500_CLKCTL1, OSEVENTTFCLKSEL, SEL, + OSEVENTTFCLKSEL_LPOSC); + g_assert_cmpuint(dev_clock_out_get_hz(CLKCTL1_NAME, "ostimer_clk"), = =3D=3D, + LPOSC_CLK_HZ); + + /* select 32khz RTC */ + REG32_WRITE_FIELD(RT500_CLKCTL1, OSEVENTTFCLKSEL, SEL, + OSEVENTTFCLKSEL_32KHZRTC); + g_assert_cmpuint(dev_clock_out_get_hz(CLKCTL1_NAME, "ostimer_clk"), = =3D=3D, + RTC32KHZ_CLK_HZ); + + /* select hclk */ + REG32_WRITE_FIELD(RT500_CLKCTL1, OSEVENTTFCLKSEL, SEL, + OSEVENTTFCLKSEL_HCLK); + g_assert_cmpuint(dev_clock_out_get_hz(CLKCTL1_NAME, "ostimer_clk"), = =3D=3D, + SYSCLK_HZ); + + /* disable clock */ + REG32_WRITE_FIELD(RT500_CLKCTL1, OSEVENTTFCLKSEL, SEL, + OSEVENTTFCLKSEL_NONE); + g_assert_cmpuint(dev_clock_out_get_hz(CLKCTL1_NAME, "ostimer_clk"), = =3D=3D, 0); +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + + qtest_add_data_func("/rt500-clkctl/pscctl-test", NULL, pscctl_test); + qtest_add_data_func("/rt500-clkctl/syspll0pfd-test", NULL, + syspll0pfd_test); + qtest_add_data_func("/rt500-clkctl/audiopll0pfd-test", NULL, + audiopll0pfd_test); + g_test_add_data_func("/rt500-clkctl/systick-test", NULL, + systick_clk_test); + g_test_add_data_func("/rt500-clkctl/ostimer-clk-test", NULL, + ostimer_clk_test); + + qtest_start("-M rt595-evk"); + ret =3D g_test_run(); + qtest_end(); + + return ret; +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index d3bf33b855..1a2d2ca3e1 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -234,6 +234,7 @@ qtests_arm =3D \ (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and config_all_devices.has_key('CONFIG_DM163')? ['dm163-test'] : []) + \ (config_all_devices.has_key('CONFIG_FLEXCOMM') ? ['flexcomm-test', 'flex= comm-usart-test', 'flexcomm-i2c-test', 'flexcomm-spi-test'] : []) + \ + (config_all_devices.has_key('CONFIG_RT500_CLKCTL') ? ['rt500-clkctl-test= '] : []) + \ ['arm-cpu-features', 'boot-serial-test'] =20 --=20 2.47.0.rc0.187.ge670bccf7e-goog