From nobody Sat Nov 23 23:34:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1728272125; cv=none; d=zohomail.com; s=zohoarc; b=CjURFGZC3TiwthXlsNBWtSTX8WepSCs445vF0S+T2bq4L0EWNG4jPAL38QomhKY5+ye1GnAkUrn6xL/lyaRXq1j9AfG8FBwAMwXjdN1Qr+MXwaiVdqac2KPTFUzsizz+vg3AZk8aIlp1Gi0pEnNVxq8IOUlqCcWw49ANj2j45AY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1728272125; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QFlizzQXd2Vzk0KL2AZvVmfiBZ91I9MAYtLOcFJEyXA=; b=H9d1mML33DPAh4cAoQ0s3C9XD6PZwsyPfbXnqKRyV7tF1/GDWrupxR5b8d0jSelSAoSGrWKYuW75sR9iaPimTh+xKKAnhswrgheG5sOLiknYIqjlfa4StkJW7+NPuKDVCAp4LgWBOppUWhLKQngw207gjHnAHiQBOufn/vpQIms= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1728272125923430.9812657626254; Sun, 6 Oct 2024 20:35:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sxeWR-0005J1-SZ; Sun, 06 Oct 2024 23:34:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sxeWP-0005Im-So; Sun, 06 Oct 2024 23:34:57 -0400 Received: from out30-97.freemail.mail.aliyun.com ([115.124.30.97]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sxeWM-00064w-VJ; Sun, 06 Oct 2024 23:34:57 -0400 Received: from localhost.localdomain(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0WGLRZQe_1728272088) by smtp.aliyun-inc.com; Mon, 07 Oct 2024 11:34:49 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1728272090; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=QFlizzQXd2Vzk0KL2AZvVmfiBZ91I9MAYtLOcFJEyXA=; b=H3Nnf3k6u9vD4HKXcHaNtIekmBka9aktT/KK+j0tA47QEnI+XnseZ+qPsvSGAjLMKIHwuuGYaSGQA8rNMnXi1mHoe8wsRpKI0373RaL+4yQNq3Za/Z/6AV+luLRbfKOYnBUUlSFZyoMgH7a6rSlJ6m1Tj0V2oqJgZunIvi6f2Wc= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng Subject: [PATCH v1 1/7] target/riscv: Fix sstatus read and write Date: Mon, 7 Oct 2024 11:33:54 +0800 Message-Id: <20241007033400.50163-2-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241007033400.50163-1-zhiwei_liu@linux.alibaba.com> References: <20241007033400.50163-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.97; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-97.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1728272128609116600 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng Sstatus is SXLEN bits in length and always has the layout determined by the SXL configuration, regardless of the current XLEN. Signed-off-by: TANG Tiancheng Fixes: b550f89457 (target/riscv: Compute mstatus.sd on demand) Fixes: f310df58bd (target/riscv: Enable uxl field write) Reviewed-by: Alistair Francis --- target/riscv/csr.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ea3560342c..b33cc1ec23 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2893,7 +2893,7 @@ static RISCVException read_sstatus_i128(CPURISCVState= *env, int csrno, { uint64_t mask =3D sstatus_v1_10_mask; uint64_t sstatus =3D env->mstatus & mask; - if (env->xl !=3D MXL_RV32 || env->debugger) { + if (riscv_cpu_sxl(env) !=3D MXL_RV32 || env->debugger) { mask |=3D SSTATUS64_UXL; } =20 @@ -2905,11 +2905,10 @@ static RISCVException read_sstatus(CPURISCVState *e= nv, int csrno, target_ulong *val) { target_ulong mask =3D (sstatus_v1_10_mask); - if (env->xl !=3D MXL_RV32 || env->debugger) { + if (riscv_cpu_sxl(env) !=3D MXL_RV32 || env->debugger) { mask |=3D SSTATUS64_UXL; } - /* TODO: Use SXL not MXL. */ - *val =3D add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); + *val =3D add_status_sd(riscv_cpu_sxl(env), env->mstatus & mask); return RISCV_EXCP_NONE; } =20 @@ -2918,7 +2917,7 @@ static RISCVException write_sstatus(CPURISCVState *en= v, int csrno, { target_ulong mask =3D (sstatus_v1_10_mask); =20 - if (env->xl !=3D MXL_RV32 || env->debugger) { + if (riscv_cpu_sxl(env) !=3D MXL_RV32 || env->debugger) { if ((val & SSTATUS64_UXL) !=3D 0) { mask |=3D SSTATUS64_UXL; } --=20 2.43.0 From nobody Sat Nov 23 23:34:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1728272143; cv=none; d=zohomail.com; s=zohoarc; b=RZ/Oupj9Aznp2czF3OfV54r9yTGnw64dnPs9SI/IvxolwyH12N/mL49Mv1ZigxqXmrvum9BsszyTTyg5a9Q6YC8xtas5t2Dq8Z+td8JCoBCYn6ikIUhhxA30johhMWyejZHMNkJQ5kf1ezAC5QlMhf2beBdcV4CE+fLFfO2tF6A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1728272143; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZK8IihrJgq1aqOhIVgrYyLKYrkCn5+LTqtDMLZVNDLE=; b=LHPJHjN/rYHiHG8sany3Kccdsiehfj2PzLaQLQ8AFelzh2azrf/dBy3iEDBm6n/zfT8QKc4Cttj3BnuhwKAwi+q+vcABTxZPq6yt44ASc7DLs2qbhIDAJvXwtBXrtGEc7EgyBtjXBGGBv2Ox0XFuPmfy41jF/5O1sgnHhB7CDW8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1728272143196552.5854700169398; Sun, 6 Oct 2024 20:35:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sxeWu-0005qZ-Ek; Sun, 06 Oct 2024 23:35:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sxeWs-0005mp-HD; Sun, 06 Oct 2024 23:35:26 -0400 Received: from out30-97.freemail.mail.aliyun.com ([115.124.30.97]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sxeWq-0006Hl-Gp; Sun, 06 Oct 2024 23:35:26 -0400 Received: from localhost.localdomain(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0WGLTm4l_1728272119) by smtp.aliyun-inc.com; Mon, 07 Oct 2024 11:35:20 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1728272121; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=ZK8IihrJgq1aqOhIVgrYyLKYrkCn5+LTqtDMLZVNDLE=; b=UlOsrOp/8zigBhOhHmZ3KAYdNwk9VrcK8Ov7DgOmz7VvwCn3sLv3C58jgqtjcUtCCj3N5F5Alo8PlBB+Y2E1MWtIpsxetu3AIUKWMjegKiAFlnp6ylZCwKYt9qyNF+0igqWKdaKpdNNHCZN66DpdcNiEpsgy/onIiGDOvYq2In8= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng , Liu Zhiwei Subject: [PATCH v1 2/7] target/riscv: Fix satp read and write implicitly or explicitly. Date: Mon, 7 Oct 2024 11:33:55 +0800 Message-Id: <20241007033400.50163-3-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241007033400.50163-1-zhiwei_liu@linux.alibaba.com> References: <20241007033400.50163-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.97; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-97.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1728272145671116600 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng CSR satp is SXLEN bits in length and always has the $layout determined by the SXL configuration, regardless of the current XLEN. Only process CSR satp, as we still don't have a riscv_cpu_vsxl API currently. Added sxl32 property to control sxlen as 32 in s-mode for QEMU RV64. Signed-off-by: TANG Tiancheng Fixes: c7b9517188 (RISC-V: Implement modular CSR helper interface) Reviewed-by: Liu Zhiwei --- target/riscv/cpu_cfg.h | 4 ++++ target/riscv/csr.c | 25 +++++++++++++++++++------ 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 8b272fb826..cdbd2afe29 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -173,6 +173,10 @@ struct RISCVCPUConfig { bool short_isa_string; =20 #ifndef CONFIG_USER_ONLY + /* + * true when RV64 QEMU running with mxlen=3D=3D64 but sxlen=3D=3D32. + */ + bool sxl32; RISCVSATPMap satp_mode; #endif }; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b33cc1ec23..93a5cf87ed 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1504,16 +1504,29 @@ static RISCVException read_mstatus(CPURISCVState *e= nv, int csrno, =20 static bool validate_vm(CPURISCVState *env, target_ulong vm) { - uint64_t mode_supported =3D riscv_cpu_cfg(env)->satp_mode.map; + uint64_t mode_supported =3D 0; + if (riscv_cpu_cfg(env)->sxl32 && (riscv_cpu_mxl(env) !=3D MXL_RV32)) { + mode_supported =3D (1 << VM_1_10_MBARE) | (1 << VM_1_10_SV32); + } else { + mode_supported =3D riscv_cpu_cfg(env)->satp_mode.map; + } return get_field(mode_supported, (1 << vm)); } =20 static target_ulong legalize_xatp(CPURISCVState *env, target_ulong old_xat= p, - target_ulong val) + target_ulong val, int csrno) { target_ulong mask; bool vm; - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + RISCVMXL xl; + + if (csrno =3D=3D CSR_SATP) { + xl =3D riscv_cpu_sxl(env); + } else { + xl =3D riscv_cpu_mxl(env); + } + + if (xl =3D=3D MXL_RV32) { vm =3D validate_vm(env, get_field(val, SATP32_MODE)); mask =3D (val ^ old_xatp) & (SATP32_MODE | SATP32_ASID | SATP32_PP= N); } else { @@ -3316,7 +3329,7 @@ static RISCVException write_satp(CPURISCVState *env, = int csrno, return RISCV_EXCP_NONE; } =20 - env->satp =3D legalize_xatp(env, env->satp, val); + env->satp =3D legalize_xatp(env, env->satp, val, csrno); return RISCV_EXCP_NONE; } =20 @@ -3834,7 +3847,7 @@ static RISCVException read_hgatp(CPURISCVState *env, = int csrno, static RISCVException write_hgatp(CPURISCVState *env, int csrno, target_ulong val) { - env->hgatp =3D legalize_xatp(env, env->hgatp, val); + env->hgatp =3D legalize_xatp(env, env->hgatp, val, csrno); return RISCV_EXCP_NONE; } =20 @@ -4116,7 +4129,7 @@ static RISCVException read_vsatp(CPURISCVState *env, = int csrno, static RISCVException write_vsatp(CPURISCVState *env, int csrno, target_ulong val) { - env->vsatp =3D legalize_xatp(env, env->vsatp, val); + env->vsatp =3D legalize_xatp(env, env->vsatp, val, csrno); return RISCV_EXCP_NONE; } =20 --=20 2.43.0 From nobody Sat Nov 23 23:34:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; 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c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1728272152; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=1NzQGwouVfdUIXxYtTl0qsxrrGtbt73O6bVWAN6aT1A=; b=ZiYyV/AoKDEcB//SGUV5UrMxIPHOhVvUe81zQw8OIZoCrjhfQUZ+4wyKx8B+/UFNpBUT3873OSvFQ39fZo6uBhd7aOR5k4v4321WhKh9pgASSpL8q3Fvzanmr+Ub4qnfoD+B1HtNrBBveDxozRu29+DVDS9mVBJbVGcU0gRdl1w= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng Subject: [PATCH v1 3/7] target/riscv: Read pte and satp based on SXL in PTW Date: Mon, 7 Oct 2024 11:33:56 +0800 Message-Id: <20241007033400.50163-4-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241007033400.50163-1-zhiwei_liu@linux.alibaba.com> References: <20241007033400.50163-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Satp and PTE are always SXLEN-bit. when SXLEN is 32, read PTE as 4 bytes, and treat satp as SATP32. Signed-off-by: TANG Tiancheng Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 077f6d77c3..773789e02e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -851,7 +851,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, vm =3D get_field(env->vsatp, SATP64_MODE); } } else { - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { base =3D (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHI= FT; vm =3D get_field(env->satp, SATP32_MODE); } else { @@ -972,7 +972,7 @@ restart: return TRANSLATE_PMP_FAIL; } =20 - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { pte =3D address_space_ldl(cs->as, pte_addr, attrs, &res); } else { pte =3D address_space_ldq(cs->as, pte_addr, attrs, &res); --=20 2.43.0 From nobody Sat Nov 23 23:34:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1728272206; cv=none; d=zohomail.com; s=zohoarc; b=cYVIFNCjB2dok+XZQQs/uwxuRcrTZfvCT1gMbiJjl6fWf96L6Q00dLdMIu4HQixBCnCWE21IW0/Xhz4S2ZdDWNMfuOylmaBSJWoOZ4p545yLOeGyvgj8OX9HM112Y8yRJuNtlNnWloXulc7fzzOemhdLcPyYBmYBVupRB1EdcW0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1728272206; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=l0oxo6n3yJSrkw/6cRUOpk9Q54Huq5YH2X/aWz0OdsQ=; b=OxQQywIw/fXhkmdQ8As4yOTDh5poOQavJcY/tku/ZXD6pEG07ZCTdXID7LbS4auWlkzjx2siuZcyhR2IsurHa5+JnAsmRX5+0oZR3bS32MOvOEXpo2TS0TsIet9+EkaVpjOeJL6wyrDz13nAwIk9rm4nX+VAVquV1VBaEDx5KkA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1728272206788774.4238856389802; Sun, 6 Oct 2024 20:36:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sxeXv-0007a4-1k; Sun, 06 Oct 2024 23:36:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sxeXt-0007ZD-Ff; Sun, 06 Oct 2024 23:36:29 -0400 Received: from out30-132.freemail.mail.aliyun.com ([115.124.30.132]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sxeXr-0006M8-G8; Sun, 06 Oct 2024 23:36:29 -0400 Received: from localhost.localdomain(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0WGLRaF9_1728272181) by smtp.aliyun-inc.com; Mon, 07 Oct 2024 11:36:22 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1728272183; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=l0oxo6n3yJSrkw/6cRUOpk9Q54Huq5YH2X/aWz0OdsQ=; b=SZSI03B90nAI9lHOsiNEi5Hwbv0y8hz54wtIQzXKj68dW86XApjB1FdF2YkOdT6aupbmkrM/T5tgXlBkAq4La9lat+0jNCgfRaFaN5AseSRLtbUgUQaD6VO5MIEVEk0UP++Yr0oFfnXsrea/QuncQllcZiyB7FCstCGW1a/4rQM= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng Subject: [PATCH v1 4/7] hw/riscv: Align kernel to 4MB when sxl32 is on. Date: Mon, 7 Oct 2024 11:33:57 +0800 Message-Id: <20241007033400.50163-5-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241007033400.50163-1-zhiwei_liu@linux.alibaba.com> References: <20241007033400.50163-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.132; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-132.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1728272207787116600 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng RISC-V always requires 4MB alignment for RV32. Signed-off-by: TANG Tiancheng --- hw/riscv/boot.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 1a2c1ff9e0..7ce0d8f08f 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -69,7 +69,8 @@ char *riscv_plic_hart_config_string(int hart_count) =20 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, target_ulong firmware_end_addr) { - if (riscv_is_32bit(harts)) { + RISCVCPU *cpu =3D &harts->harts[0]; + if (riscv_is_32bit(harts) || cpu->cfg.sxl32) { return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); } else { return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); --=20 2.43.0 From nobody Sat Nov 23 23:34:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; 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charset="utf-8" From: TANG Tiancheng Allow reading 32-bit only registers like timeh and stimecmph when booting a 32-bit Linux kernel on RV64 when sxl32 is true. Signed-off-by: TANG Tiancheng --- target/riscv/csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 93a5cf87ed..c412ac8e31 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -161,7 +161,7 @@ skip_ext_pmu_check: =20 static RISCVException ctr32(CPURISCVState *env, int csrno) { - if (riscv_cpu_mxl(env) !=3D MXL_RV32) { + if (env->xl !=3D MXL_RV32) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -481,7 +481,7 @@ static RISCVException sstc(CPURISCVState *env, int csrn= o) =20 static RISCVException sstc_32(CPURISCVState *env, int csrno) { - if (riscv_cpu_mxl(env) !=3D MXL_RV32) { + if (env->xl !=3D MXL_RV32) { return RISCV_EXCP_ILLEGAL_INST; } =20 --=20 2.43.0 From nobody Sat Nov 23 23:34:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: TANG Tiancheng When boot a 32-bit system, sxl and uxl should be set to 1 by OpenSBI. Howev= er, OpenSBI does not support this feature. We temporarily force QEMU reset SXL and UXL to MXL_RV32 when sxl32 is enabl= ed. Signed-off-by: TANG Tiancheng --- target/riscv/cpu.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index baf8fba467..9dbbb1ca77 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -933,8 +933,17 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTyp= e type) * The reset status of SXL/UXL is undefined, but mstatus is WARL * and we must ensure that the value after init is valid for read. */ - env->mstatus =3D set_field(env->mstatus, MSTATUS64_SXL, env->misa_= mxl); - env->mstatus =3D set_field(env->mstatus, MSTATUS64_UXL, env->misa_= mxl); + if (cpu->cfg.sxl32) { + env->mstatus =3D set_field(env->mstatus, MSTATUS64_SXL, + MXL_RV32); + env->mstatus =3D set_field(env->mstatus, MSTATUS64_UXL, + MXL_RV32); + } else { + env->mstatus =3D set_field(env->mstatus, MSTATUS64_SXL, + env->misa_mxl); + env->mstatus =3D set_field(env->mstatus, MSTATUS64_UXL, + env->misa_mxl); + } if (riscv_has_ext(env, RVH)) { env->vsstatus =3D set_field(env->vsstatus, MSTATUS64_SXL, env->misa_mxl); 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Mon, 07 Oct 2024 12:09:14 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1728274155; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=E2twuR14LYSGtq8m/vSLS1GgHxOHXTDk0j0rsNDxxBE=; b=W9vk+JqyTx/l8bKPh0JvWRjYuTR24uFd/8DUaasAVeHMPKPEQR6Kzgq8TbN7h8eXpvHaLl54A5sy2L8vqUiexTTujR5kYH7DKQoZag7t1LIhzLms7ZEbhjmlLK6FnGGQwb5gzWZsivAm7ZQqASV335iTY1omjvC3eq9mt/cfVns= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng Subject: [PATCH v1 7/7] target/riscv: Expose sxl32 configuration in RISC-V CPU Date: Mon, 7 Oct 2024 11:34:00 +0800 Message-Id: <20241007033400.50163-8-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241007033400.50163-1-zhiwei_liu@linux.alibaba.com> References: <20241007033400.50163-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Enable with "-cpu rv64,sxl32=3Don". When sxl32 is enabled, RV64 can boot 32-bit Linux with 64-bit Opensbi while requiring to make minor modifications to the Linux kernel source code. How to patch linux: https://git Signed-off-by: TANG Tiancheng --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9dbbb1ca77..86984b7f8f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2665,6 +2665,7 @@ static Property riscv_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), + DEFINE_PROP_BOOL("sxl32", RISCVCPU, cfg.sxl32, false), #endif =20 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, f= alse), --=20 2.43.0