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Mon, 07 Oct 2024 10:59:08 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1728269950; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=w8Lx1g9UTqUJw4++FBNmopFsdQHo5Omd6l7285PLmsQ=; b=BlvB5yNCkohe+t0JeWDEKDpVx6HfndAQemsvsHBoLVZgtanJx6vZ+eDqPe24+wkM1zm5LFlHRdQ5bW8K9yc8nERKj+KMexeMWBnx2h82IHYEi9CzNCkB1ZGlC8u7FQFaxWP+Ol50sOhB/4FdJGRDCF8x4f/STXOC2aIMtoEuYYw= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, richard.henderson@linaro.org, TANG Tiancheng , Liu Zhiwei Subject: [PATCH v5 04/12] tcg/riscv: Implement vector mov/dup{m/i} Date: Mon, 7 Oct 2024 10:56:52 +0800 Message-Id: <20241007025700.47259-5-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241007025700.47259-1-zhiwei_liu@linux.alibaba.com> References: <20241007025700.47259-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 73 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 71 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index aacb1ae28e..5187cdb6ac 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -309,6 +309,12 @@ typedef enum { OPC_VS2R_V =3D 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(1), OPC_VS4R_V =3D 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(3), OPC_VS8R_V =3D 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(7), + + OPC_VMV_V_V =3D 0x5e000057 | V_OPIVV, + OPC_VMV_V_I =3D 0x5e000057 | V_OPIVI, + OPC_VMV_V_X =3D 0x5e000057 | V_OPIVX, + + OPC_VMVNR_V =3D 0x9e000057 | V_OPIVI, } RISCVInsn; =20 /* @@ -401,6 +407,16 @@ static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uin= t32_t imm) return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm); } =20 + +/* Type-OPIVI */ + +static int32_t encode_vi(RISCVInsn opc, TCGReg rd, int32_t imm, + TCGReg vs2, bool vm) +{ + return opc | (rd & 0x1f) << 7 | (imm & 0x1f) << 15 | + (vs2 & 0x1f) << 20 | (vm << 25); +} + /* Type-OPIVV/OPMVV/OPIVX/OPMVX, Vector load and store */ =20 static int32_t encode_v(RISCVInsn opc, TCGReg d, TCGReg s1, @@ -546,6 +562,24 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, * RISC-V vector instruction emitters */ =20 +/* + * Vector registers uses the same 5 lower bits as GPR registers, + * and vm=3D0 (vm =3D false) means vector masking ENABLED. + * With RVV 1.0, vs2 is the first operand, while rs1/imm is the + * second operand. + */ +static void tcg_out_opc_vx(TCGContext *s, RISCVInsn opc, TCGReg vd, + TCGReg vs2, TCGReg rs1, bool vm) +{ + tcg_out32(s, encode_v(opc, vd, rs1, vs2, vm)); +} + +static void tcg_out_opc_vi(TCGContext *s, RISCVInsn opc, TCGReg vd, + TCGReg vs2, int32_t imm, bool vm) +{ + tcg_out32(s, encode_vi(opc, vd, imm, vs2, vm)); +} + /* * Only unit-stride addressing implemented; may extend in future. */ @@ -628,6 +662,13 @@ static MemOp set_vtype_len(TCGContext *s, TCGType type) return s->riscv_cur_vsew; } =20 +static void set_vtype_len_sew(TCGContext *s, TCGType type, MemOp vsew) +{ + if (type !=3D s->riscv_cur_type || vsew !=3D s->riscv_cur_vsew) { + set_vtype(s, type, vsew); + } +} + /* * TCG intrinsics */ @@ -642,6 +683,15 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, T= CGReg ret, TCGReg arg) case TCG_TYPE_I64: tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); break; + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + { + int lmul =3D type - riscv_lg2_vlenb; + int nf =3D 1 << MAX(lmul, 0); + tcg_out_opc_vi(s, OPC_VMVNR_V, ret, arg, nf - 1, true); + } + break; default: g_assert_not_reached(); } @@ -1005,18 +1055,32 @@ static void tcg_out_addsub2(TCGContext *s, static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src) { - return false; + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vx(s, OPC_VMV_V_X, dst, TCG_REG_V0, src, true); + return true; } =20 static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg base, intptr_t offs= et) { - return false; + tcg_out_ld(s, TCG_TYPE_REG, TCG_REG_TMP0, base, offset); + return tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0); } =20 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, int64_t arg) { + if (arg >=3D -16 && arg < 16) { + if (arg =3D=3D 0 || arg =3D=3D -1) { + set_vtype_len(s, type); + } else { + set_vtype_len_sew(s, type, vece); + } + tcg_out_opc_vi(s, OPC_VMV_V_I, dst, TCG_REG_V0, arg, true); + return; + } + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, arg); + tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0); } =20 static const struct { @@ -2159,6 +2223,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, a2 =3D args[2]; =20 switch (opc) { + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + break; case INDEX_op_ld_vec: tcg_out_ld(s, type, a0, a1, a2); break; @@ -2330,6 +2397,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) =20 case INDEX_op_st_vec: return C_O0_I2(v, r); + case INDEX_op_dup_vec: + case INDEX_op_dupm_vec: case INDEX_op_ld_vec: return C_O1_I1(v, r); default: --=20 2.43.0