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Mon, 07 Oct 2024 11:01:44 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1728270106; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=1BwZTo2Gv9JmjGRLj61qhmQffATv4Z1KiVQQa2ozVQQ=; b=nFTGs4FfOaH/L1vSvpLSVADYKb9OBUgXcsRZUYMyIxRCdqMe7LYSCRX7AX44z9bA1zX0omwebwgIRTmqmHlV2Fw9VZweKxUshQkb5Gmge1sJMiVuP4p/MnpBrVzSdMRHAzURpn0f849TJWw1LW3naLoWySX8/IeRNIx2PdHHN0c= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, richard.henderson@linaro.org, TANG Tiancheng , Liu Zhiwei Subject: [PATCH v5 09/12] tcg/riscv: Implement vector min/max ops Date: Mon, 7 Oct 2024 10:56:57 +0800 Message-Id: <20241007025700.47259-10-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241007025700.47259-1-zhiwei_liu@linux.alibaba.com> References: <20241007025700.47259-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 29 +++++++++++++++++++++++++++++ tcg/riscv/tcg-target.h | 2 +- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 0b2541692a..fd9a079d53 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -287,6 +287,11 @@ typedef enum { OPC_VSADDU_VV =3D 0x80000057 | V_OPIVV, OPC_VSSUBU_VV =3D 0x88000057 | V_OPIVV, =20 + OPC_VMAX_VV =3D 0x1c000057 | V_OPIVV, + OPC_VMAXU_VV =3D 0x18000057 | V_OPIVV, + OPC_VMIN_VV =3D 0x14000057 | V_OPIVV, + OPC_VMINU_VV =3D 0x10000057 | V_OPIVV, + OPC_VMSEQ_VV =3D 0x60000057 | V_OPIVV, OPC_VMSEQ_VI =3D 0x60000057 | V_OPIVI, OPC_VMSEQ_VX =3D 0x60000057 | V_OPIVX, @@ -2432,6 +2437,22 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, set_vtype_len_sew(s, type, vece); tcg_out_opc_vv(s, OPC_VSSUBU_VV, a0, a1, a2, true); break; + case INDEX_op_smax_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv(s, OPC_VMAX_VV, a0, a1, a2, true); + break; + case INDEX_op_smin_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv(s, OPC_VMIN_VV, a0, a1, a2, true); + break; + case INDEX_op_umax_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv(s, OPC_VMAXU_VV, a0, a1, a2, true); + break; + case INDEX_op_umin_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv(s, OPC_VMINU_VV, a0, a1, a2, true); + break; case INDEX_op_cmpsel_vec: tcg_out_cmpsel(s, type, vece, args[5], a0, a1, a2, const_args[2], args[3], const_args[3], args[4], const_args[4]); @@ -2481,6 +2502,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: case INDEX_op_cmpsel_vec: return 1; case INDEX_op_cmp_vec: @@ -2648,6 +2673,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return C_O1_I2(v, v, v); case INDEX_op_cmp_vec: return C_O1_I2(v, v, vL); diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 1d4d8878ce..7005099810 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -162,7 +162,7 @@ typedef enum { #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 -#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 1 =20 --=20 2.43.0