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[217.94.215.144]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f86a0afc1sm47506775e9.1.2024.10.05.12.47.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 12:47:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1728157625; x=1728762425; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uWbe6sy8YDQU8OuL8fDc3zUrDVgXUCz7bTnLrmpVA0c=; b=O+OL3r9QYCrYfNcG1Pt0yZMY2yRizxOSDqeiDYg9t49SAKVI8x9hvCRKpFfRxq9fdU TngPFio9VKKhvFZZIDd6M/uPtHtM/HljOKT/jE1rMS4Ga+FPnyVerFnzMNC2DgsXgjWN bDIrVFoK9790tFf8ubFelqgPQoizQm0exg5bQxf9sLqYsCUrqBHZx4xf28GmIBg+t+ap 1JPmeBltUoiouy1U866I3dbT388h0a5iyzio82fEHL8DjJMyZNNLpyz2VPkzckdvwW+T wxWtZw+cSYVbqc2sKPn96AOMf0i+SXF470LV8HxIa21gEi3atiVcEg+ihB6xT5IGaJZt jZ7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728157625; x=1728762425; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uWbe6sy8YDQU8OuL8fDc3zUrDVgXUCz7bTnLrmpVA0c=; b=LNRt3H9PvttWAziXp02dzqOVLyN8R1fmWjiDJVF1rafIzretAGeP7iE5qw8DBE3rAz 9Fu3dE2/+xQiW6zwWpiAoPxJy8IUkc6phVGkeiiko2Bzy7UmUELH5gaQpnYUAlpx2SAv Dggn1BstQgr+Et3OuzAs2lprXKPlIx/jgQMIZzz/vvystb+Fz+Xxatubm3pEcIihZVxi ijcKejiz5x+A1mDvjOjZWP55io84jqaRCTI9ah8ebkiYpP5PyWpa/23I1m65FzM4bG6K oX0CLkXA43NueEcBN6XdAC5A1ZdaMrtCjh9rdlihRzZ5H/nYfn6JDyGkxGvRLwnZqdIC Vvkw== X-Forwarded-Encrypted: i=1; AJvYcCUg8/6Bnz51uy8g7J7tIcJEstW7oBRimgJJmU9mlBkzBk/tb/FgY/z+yjug5w3N4dyuTSQHfJmTuecl@nongnu.org, AJvYcCV4ndNss7rP94KnQ7KWp+32pEvVC+GsPog438EUy4Sq4krjZwpzVzPVq+/AofyE+6T/5djbKbVP03k=@nongnu.org X-Gm-Message-State: AOJu0YxurlrtV/IkFJX1oCpEkFisydt6/b+TJoLxx+KIhSgnIBN/vx2S zAfYMYmoUiIMjV7MkMRbMKsX/aNpFa5x2TfFavTlwokUu94o62hgYbxhAQ== X-Google-Smtp-Source: AGHT+IG5g/rsq9seolLBlh/Iqe5qaVV5+tjlHe8Xnxx7UcmMrtqBcKJyRcVGC6FR0cLODd8FhnXWgA== X-Received: by 2002:a05:600c:4e86:b0:42f:5ca3:d784 with SMTP id 5b1f17b1804b1-42f85aae76dmr59578575e9.14.1728157624561; Sat, 05 Oct 2024 12:47:04 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Daniel Henrique Barboza , Nicholas Piggin , Bin Meng , Corey Minyard , Bernhard Beschow , qemu-ppc@nongnu.org, Alex Williamson , Hanna Reitz , Jason Wang , qemu-block@nongnu.org, Kevin Wolf , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 08/23] hw/ppc/ppce500_ccsr: Log access to unimplemented registers Date: Sat, 5 Oct 2024 21:45:48 +0200 Message-ID: <20241005194603.23139-9-shentey@gmail.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241005194603.23139-1-shentey@gmail.com> References: <20241005194603.23139-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=shentey@gmail.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1728157763298116600 Content-Type: text/plain; charset="utf-8" The CCSR space is just a container which is meant to be covered by platform device memory regions. However, QEMU only implements a subset of these devi= ces. Add some logging to see which devices a guest attempts to access. Signed-off-by: Bernhard Beschow --- hw/ppc/ppce500_ccsr.c | 32 +++++++++++++++++++++++++++++++- hw/ppc/trace-events | 3 +++ 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/hw/ppc/ppce500_ccsr.c b/hw/ppc/ppce500_ccsr.c index 5d0e1e0e89..6659560674 100644 --- a/hw/ppc/ppce500_ccsr.c +++ b/hw/ppc/ppce500_ccsr.c @@ -13,12 +13,42 @@ =20 #include "qemu/osdep.h" #include "ppce500_ccsr.h" +#include "qemu/log.h" +#include "trace.h" + +static uint64_t ppce500_ccsr_io_read(void *opaque, hwaddr addr, unsigned s= ize) +{ + uint64_t value =3D 0; + + trace_ppce500_ccsr_io_read(addr, value, size); + qemu_log_mask(LOG_UNIMP, + "%s: unimplemented [0x%" HWADDR_PRIx "] -> 0\n", + __func__, addr); + + return value; +} + +static void ppce500_ccsr_io_write(void *opaque, hwaddr addr, uint64_t valu= e, + unsigned size) +{ + trace_ppce500_ccsr_io_write(addr, value, size); + qemu_log_mask(LOG_UNIMP, + "%s: unimplemented [0x%" HWADDR_PRIx "] <- 0x%" PRIx32 "= \n", + __func__, addr, (uint32_t)value); +} + +static const MemoryRegionOps ppce500_ccsr_ops =3D { + .read =3D ppce500_ccsr_io_read, + .write =3D ppce500_ccsr_io_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; =20 static void ppce500_ccsr_init(Object *obj) { PPCE500CCSRState *s =3D CCSR(obj); =20 - memory_region_init(&s->ccsr_space, obj, "e500-ccsr", MPC85XX_CCSRBAR_S= IZE); + memory_region_init_io(&s->ccsr_space, obj, &ppce500_ccsr_ops, obj, + "e500-ccsr", MPC85XX_CCSRBAR_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->ccsr_space); } =20 diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index 1f125ce841..ca4c231c9f 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -143,6 +143,9 @@ ppc_irq_cpu(const char *action) "%s" ppc_dcr_read(uint32_t addr, uint32_t val) "DRCN[0x%x] -> 0x%x" ppc_dcr_write(uint32_t addr, uint32_t val) "DRCN[0x%x] <- 0x%x" =20 +ppce500_ccsr_io_read(uint32_t index, uint32_t val, uint8_t size) "[0x%" PR= Ix32 "] -> 0x%08x (size: 0x%" PRIu8 ")" +ppce500_ccsr_io_write(uint32_t index, uint32_t val, uint8_t size) "[0x%" P= RIx32 "] <- 0x%08x (size: 0x%" PRIu8 ")" + # prep_systemio.c prep_systemio_read(uint32_t addr, uint32_t val) "read addr=3D0x%x val=3D0x= %x" prep_systemio_write(uint32_t addr, uint32_t val) "write addr=3D0x%x val=3D= 0x%x" --=20 2.46.2