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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.25.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:25:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728141957; x=1728746757; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DH35lHXcbsJC32qCjyMaGZFqdyczAIeo1misqQjkoMQ=; b=UCh0hlAXOunMMPt9F5S8w98xbM/zSc7abiacXVRbMO3Xd9b6pXPB/zDboGURyzAvin 5VCXFLOCRSvmhu1bC1MG7Y1bXofhTZUFRdSrIpbbME/O6wMRzqgsBKmc92rdbZpm0CBo cxk+Sf4LqN1ldAQPnp9r+G9jqsCfHiwYQTKrtJC3yNlPS9lmHX83ByjiwbfmBaEaLkKq rLQ9bpgzzcwj91ajRKJXbdmicQdOXsW8t+0DWgiy0d6BwRyisMIlqMebZnILD6UzjFj1 UAhcfUycLk8OL57GgPaTgAHL1OO4nqKPGf/ExRRI+v/hPBQVpmwiJhoRluIetmW1sWpJ Lfmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728141957; x=1728746757; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DH35lHXcbsJC32qCjyMaGZFqdyczAIeo1misqQjkoMQ=; b=cDJLCNNgrKSzi86/0H+Zc9h1Jz1DSYIRh2Lz4TyMEwqX2lefc+158kWPLACj0dF4jA BkahnWeHg3g8mZPUuZIB60H6xiaxkozuGBo6Zs8IzC8H9BeRc4wiLxXrDPK3CUsEGYXt 35of90Ga7/v7xBAPSAGjBSfq4Qr5HpmsqxPGkn6LaMxSENTEhe+p5UjfTq897RoRj6m+ oIZFQm7NEZV+8TFF41NRfDjx7U2hM8FgcwYS8NJc3txNIFoeWklolWb2hoB4Q7j8/FF/ 0akhf/dWyDeRA68mUN/wV8rQbWGHPef6Y2nh78yZPH0gjoNkRtHXi0pGtVjejeAUrUxO b/tg== X-Gm-Message-State: AOJu0Yxr1QUHkJ88GSrDuRl/JtyQy1RyhK2Z7ecH36+WLMMmf2+qaZFX alO1J6U5FmcbaH3M8PYO75YsN+prlmSgNPD74Xac0FDeb7/SUHe5E33nIPkcq42gkhjwq8D5bA9 z X-Google-Smtp-Source: AGHT+IHT5o1cj1/9FCBXAXC0/1+PVD5HvqkowrTIKtKub8G3zTkYo3PO7CJQAs6NH7O9Krc3Ois1eQ== X-Received: by 2002:a17:902:e94e:b0:20b:ce4e:b9e4 with SMTP id d9443c01a7336-20bfe044af6mr97224115ad.29.1728141956662; Sat, 05 Oct 2024 08:25:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 04/20] include/exec/memop: Rename get_alignment_bits Date: Sat, 5 Oct 2024 08:25:35 -0700 Message-ID: <20241005152551.307923-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1728142041410116600 Content-Type: text/plain; charset="utf-8" Rename to use "memop_" prefix, like other functions that operate on MemOp. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/memop.h | 4 ++-- accel/tcg/cputlb.c | 4 ++-- accel/tcg/user-exec.c | 4 ++-- target/arm/tcg/translate-a64.c | 4 ++-- target/xtensa/translate.c | 2 +- tcg/tcg-op-ldst.c | 6 +++--- tcg/tcg.c | 2 +- tcg/arm/tcg-target.c.inc | 4 ++-- tcg/sparc64/tcg-target.c.inc | 2 +- 9 files changed, 16 insertions(+), 16 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index 97720a8ee7..f53bf618c6 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -171,12 +171,12 @@ static inline bool memop_big_endian(MemOp op) } =20 /** - * get_alignment_bits + * memop_alignment_bits: * @memop: MemOp value * * Extract the alignment size from the memop. */ -static inline unsigned get_alignment_bits(MemOp memop) +static inline unsigned memop_alignment_bits(MemOp memop) { unsigned a =3D memop & MO_AMASK; =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 58960969f4..b5bff220a3 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1693,7 +1693,7 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, Mem= OpIdx oi, tcg_debug_assert(l->mmu_idx < NB_MMU_MODES); =20 /* Handle CPU specific unaligned behaviour */ - a_bits =3D get_alignment_bits(l->memop); + a_bits =3D memop_alignment_bits(l->memop); if (addr & ((1 << a_bits) - 1)) { cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); } @@ -1781,7 +1781,7 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr a= ddr, MemOpIdx oi, { uintptr_t mmu_idx =3D get_mmuidx(oi); MemOp mop =3D get_memop(oi); - int a_bits =3D get_alignment_bits(mop); + int a_bits =3D memop_alignment_bits(mop); uintptr_t index; CPUTLBEntry *tlbe; vaddr tlb_addr; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 7ddc47b0ba..08a6df9987 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -959,7 +959,7 @@ void page_reset_target_data(target_ulong start, target_= ulong last) { } static void *cpu_mmu_lookup(CPUState *cpu, vaddr addr, MemOp mop, uintptr_t ra, MMUAccessType type) { - int a_bits =3D get_alignment_bits(mop); + int a_bits =3D memop_alignment_bits(mop); void *ret; =20 /* Enforce guest required alignment. */ @@ -1241,7 +1241,7 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr a= ddr, MemOpIdx oi, int size, uintptr_t retaddr) { MemOp mop =3D get_memop(oi); - int a_bits =3D get_alignment_bits(mop); + int a_bits =3D memop_alignment_bits(mop); void *ret; =20 /* Enforce guest required alignment. */ diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 071b6349fc..ec0b1ee252 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -294,7 +294,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, = TCGv_i64 addr, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc =3D FIELD_DP32(desc, MTEDESC, ALIGN, get_alignment_bits(memop= )); + desc =3D FIELD_DP32(desc, MTEDESC, ALIGN, memop_alignment_bits(mem= op)); desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, memop_size(memop) - 1); =20 ret =3D tcg_temp_new_i64(); @@ -326,7 +326,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr,= bool is_write, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc =3D FIELD_DP32(desc, MTEDESC, ALIGN, get_alignment_bits(singl= e_mop)); + desc =3D FIELD_DP32(desc, MTEDESC, ALIGN, memop_alignment_bits(sin= gle_mop)); desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1); =20 ret =3D tcg_temp_new_i64(); diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 75b7bfda4c..f4da4a40f9 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -521,7 +521,7 @@ static MemOp gen_load_store_alignment(DisasContext *dc,= MemOp mop, mop |=3D MO_ALIGN; } if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) { - tcg_gen_andi_i32(addr, addr, ~0 << get_alignment_bits(mop)); + tcg_gen_andi_i32(addr, addr, ~0 << memop_alignment_bits(mop)); } return mop; } diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 23dc807f11..a318011229 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -45,7 +45,7 @@ static void check_max_alignment(unsigned a_bits) =20 static MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) { - unsigned a_bits =3D get_alignment_bits(op); + unsigned a_bits =3D memop_alignment_bits(op); =20 check_max_alignment(a_bits); =20 @@ -559,7 +559,7 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCG= Temp *addr, TCGv_i64 ext_addr =3D NULL; TCGOpcode opc; =20 - check_max_alignment(get_alignment_bits(memop)); + check_max_alignment(memop_alignment_bits(memop)); tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); =20 /* In serial mode, reduce atomicity. */ @@ -676,7 +676,7 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCG= Temp *addr, TCGv_i64 ext_addr =3D NULL; TCGOpcode opc; =20 - check_max_alignment(get_alignment_bits(memop)); + check_max_alignment(memop_alignment_bits(memop)); tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); =20 /* In serial mode, reduce atomicity. */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 34e3056380..5decd83cf4 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -5506,7 +5506,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) static TCGAtomAlign atom_and_align_for_opc(TCGContext *s, MemOp opc, MemOp host_atom, bool allow_two= _ops) { - MemOp align =3D get_alignment_bits(opc); + MemOp align =3D memop_alignment_bits(opc); MemOp size =3D opc & MO_SIZE; MemOp half =3D size ? size - 1 : 0; MemOp atom =3D opc & MO_ATOM_MASK; diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 3de5f50b62..56072d89a2 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1587,7 +1587,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, Mem= Op opc, TCGReg datalo, tcg_debug_assert((datalo & 1) =3D=3D 0); tcg_debug_assert(datahi =3D=3D datalo + 1); /* LDRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >=3D MO_64) { + if (memop_alignment_bits(opc) >=3D MO_64) { if (h.index < 0) { tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); break; @@ -1691,7 +1691,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Mem= Op opc, TCGReg datalo, tcg_debug_assert((datalo & 1) =3D=3D 0); tcg_debug_assert(datahi =3D=3D datalo + 1); /* STRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >=3D MO_64) { + if (memop_alignment_bits(opc) >=3D MO_64) { if (h.index < 0) { tcg_out_strd_8(s, h.cond, datalo, h.base, 0); } else { diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 176c98740b..32f9ec24b5 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1133,7 +1133,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, * Otherwise, test for at least natural alignment and defer * everything else to the helper functions. */ - if (s_bits !=3D get_alignment_bits(opc)) { + if (s_bits !=3D memop_alignment_bits(opc)) { tcg_debug_assert(check_fit_tl(a_mask, 13)); tcg_out_arithi(s, TCG_REG_G0, addr_reg, a_mask, ARITH_ANDCC); =20 --=20 2.43.0