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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728141971; x=1728746771; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/ZHU/9Bj/Yhl/fLIAf9ED9KKjqQvRkGT+c+Pl2SvUJY=; b=NbCZxWDXl67vfNw5Ketw445FX8j/e3765S4th3nWnATFSoeU0iFpCPG2GYzm3XrV8V gij4rxIdteJBA7wmVPzqnNP9ZHKmMOUDgCC0tPkxdHxlq6fcmLSnpnRmQAkyf75lus6m wGpOYbqnosdLZ3rrL6uxV6oH8mDoqHBLO6wHejMg+pJ4tP6q97gCT2jIxUcRS62/8YSK PeAD+ldOp+SWwJFpbYHu+VRrrtA1c5l9EloFWyD5MzZFBrJIo6O07EsoIeguFgijZgjz 0Q02AupovWS9eNzThw72F1xaPhy3d2LRl2f6vMkBjWlW67xoULsI0juBfgKqrlyPDv8W L6Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728141971; x=1728746771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/ZHU/9Bj/Yhl/fLIAf9ED9KKjqQvRkGT+c+Pl2SvUJY=; b=eecp76kMR23tMCvjdFWBFfZcv4p/3pH2KlCAqgC/b79hKGxNh+9ZfVEfDbYKlGXyzD aMLdcqE1x32XXpfyiaK3Y38A/s5AWXZaZ8juWYH8Cv85yZNbjlZORIBkSsbwDhwESRti YcCrCq/TmF7Sb0cdn5D5iqX5RaNKkaugdhxaKTr5RN2C4WVO6caJXvR0dyBvrj2l/qlw szu17nxYkLtvyq5JmBSwYAK/ffcT/xGK78ekTL6bWDkylFy2dBr/GwgMZtwcP+kfShsg xnKJFgf03jRVU4QhI9Z5NmjTDRqhSAuaQ+Iv2gzVxn0J6KBoRWrRCaU+JTeinS4Hlc+P UNAw== X-Gm-Message-State: AOJu0Yya0hvSQrPwkIpLXm8llXtUz9WKTVovAc9RTn12+9+QdHwkiVgn drd3cm+mJ3qsznvtpR79yWAVwWRzX7UBjMCvjZUtMs9IIilnV6MPTwJD0KJcj5D/Huh1q8c8FER l X-Google-Smtp-Source: AGHT+IH4Lr64SQZfzlOO2MyBkQGMuSWCJxA1Uid5flyT3IfspQk+qHg9k3FYTQCTF9/9yq+5XQ2JSg== X-Received: by 2002:a17:903:2b07:b0:20b:8e18:a395 with SMTP id d9443c01a7336-20bfe291f03mr89154495ad.44.1728141971365; Sat, 05 Oct 2024 08:26:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 19/20] target/arm: Move device detection earlier in get_phys_addr_lpae Date: Sat, 5 Oct 2024 08:25:50 -0700 Message-ID: <20241005152551.307923-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1728142049645116600 Content-Type: text/plain; charset="utf-8" Determine cache attributes, and thence Device vs Normal memory, earlier in the function. We have an existing regime_is_stage2 if block into which this can be slotted. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 49 ++++++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 238b2c92a9..0a1a820362 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2029,8 +2029,20 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, xn =3D extract64(attrs, 53, 2); result->f.prot =3D get_S2prot(env, ap, xn, ptw->in_s1_is_el0); } + + result->cacheattrs.is_s2_format =3D true; + result->cacheattrs.attrs =3D extract32(attrs, 2, 4); + /* + * Security state does not really affect HCR_EL2.FWB; + * we only need to filter FWB for aa32 or other FEAT. + */ + device =3D S2_attrs_are_device(arm_hcr_el2_eff(env), + result->cacheattrs.attrs); } else { int nse, ns =3D extract32(attrs, 5, 1); + uint8_t attrindx; + uint64_t mair; + switch (out_space) { case ARMSS_Root: /* @@ -2102,6 +2114,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, */ result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, xn, pxn, result->f.attrs.space, out_space); + + /* Index into MAIR registers for cache attributes */ + attrindx =3D extract32(attrs, 2, 3); + mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; + assert(attrindx <=3D 7); + result->cacheattrs.is_s2_format =3D false; + result->cacheattrs.attrs =3D extract64(mair, attrindx * 8, 8); + + /* When in aarch64 mode, and BTI is enabled, remember GP in the TL= B. */ + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { + result->f.extra.arm.guarded =3D extract64(attrs, 50, 1); /* GP= */ + } + device =3D S1_attrs_are_device(result->cacheattrs.attrs); } =20 if (!(result->f.prot & (1 << access_type))) { @@ -2131,30 +2156,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, result->f.attrs.space =3D out_space; result->f.attrs.secure =3D arm_space_is_secure(out_space); =20 - if (regime_is_stage2(mmu_idx)) { - result->cacheattrs.is_s2_format =3D true; - result->cacheattrs.attrs =3D extract32(attrs, 2, 4); - /* - * Security state does not really affect HCR_EL2.FWB; - * we only need to filter FWB for aa32 or other FEAT. - */ - device =3D S2_attrs_are_device(arm_hcr_el2_eff(env), - result->cacheattrs.attrs); - } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx =3D extract32(attrs, 2, 3); - uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <=3D 7); - result->cacheattrs.is_s2_format =3D false; - result->cacheattrs.attrs =3D extract64(mair, attrindx * 8, 8); - - /* When in aarch64 mode, and BTI is enabled, remember GP in the TL= B. */ - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { - result->f.extra.arm.guarded =3D extract64(attrs, 50, 1); /* GP= */ - } - device =3D S1_attrs_are_device(result->cacheattrs.attrs); - } - /* * Enable alignment checks on Device memory. * --=20 2.43.0