From nobody Sun Nov 24 01:03:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1728142139; cv=none; d=zohomail.com; s=zohoarc; b=V6ch/4B9MQIBUqicdt/t6UaQ8NSxt5Ky++7ax2JpCQYABzcE3eKxyo3gaxTyjH5W68oxTdyPagBv+odL8huH9PS+7xt4u7dQAlkRvJdOxfnlcKojsZF2tur/alhtaxh3l3R80eOZlhbtL4KTpeN41WC1/rpKT74lgLi2lq6quJY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1728142139; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=E1uh5v8Er5HwrssIP/tcmhd1DyyVCAW+cpRhBaU0frQ=; b=OQ0TydfrUtco9uJMT4MHGV0QnloarU3eWH3//HgO2kCHSba64tDPe/OPc2PgR0Jl9uRC4WwllfYGPh89MpfqgPo2tLerQoyPZ+4I7nMZCut3smjxRXY3qrwiJ0rQzwYDChHy66DOw/ynaEEGbQRb2NK5gKtNr9TVUrk7GMwAR9A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1728142139859874.749071988613; Sat, 5 Oct 2024 08:28:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sx6fh-0002Bn-W7; Sat, 05 Oct 2024 11:26:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sx6fZ-000268-Lv for qemu-devel@nongnu.org; Sat, 05 Oct 2024 11:26:11 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sx6fW-0002OT-Od for qemu-devel@nongnu.org; Sat, 05 Oct 2024 11:26:09 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-20b833f9b35so26761655ad.2 for ; Sat, 05 Oct 2024 08:26:06 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728141965; x=1728746765; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E1uh5v8Er5HwrssIP/tcmhd1DyyVCAW+cpRhBaU0frQ=; b=XSf6isPkETO/Z+QHvF5QsoGZKhS3bQ5aJYcxrXaEPv1JOvpW5a1IciamZcKUBI+ITX x6B9vo2otJVBz3tRUo+MgdQyVEM0LepWBERaiClL/W3RQiEF7Bgl4tB4ohMMRcFYC850 L5rYwgX5320OWuu81ez6Q+byKnHi3gYO8b7AruPUMmeDmuLkqHg9gLRaAxWkEC7B5Fm1 VrA4m9PrqztE9zbYXF+dLxAianCY/5ov+267WnbaicuJ4t6onV9hrejx2ZOXZgs+XxX5 3dw+78iZJrL2VxxgdwpT9O4Kcqgbe1h7PAG5swcfL0CH62VPegoZjMRAauy81Ngil+PO LJiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728141965; x=1728746765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E1uh5v8Er5HwrssIP/tcmhd1DyyVCAW+cpRhBaU0frQ=; b=PUf22U3S1Cs50XySNAJ4Yuwlf9fFqDXlKa4ZzvlNk1hbKSaQk+BeRiSpKdxKFa3jkt MktkYj3EVpxtyPHj4GbIFy/ta0bqHKgwptim9maLoSGbLl/a9TEEW/uhb7Ge6O7HAoIw 5IMWGIXR3f6u3Ipzm1T93uvk/wx2k4A8Ld2ofdntgHyPPwuMA5Dglo5PreYGrUxfoNgp FxbnhcOKshl/wDsuGZXHFYWMuwixO0yY3fXaJil3er+fF6BtCKgrFdUbUjNzYqRsKCFg B8UwBc3Vc8tH3VA9dpyqSe59mb3DjMOFOsk5Y0HQUH4cY5OAGnlwWi5TYBq8Cq+Ad3o6 4cMQ== X-Gm-Message-State: AOJu0Yz0CcR8ROt1ssOiEHsf7W9lJN9WcRy7WcXZZqST3RucuJRsr7jZ dwdNYPj2M99oExPi29vtkqMfCtr/vgLePunLyx2tFYbY+2snASZZInGYFcE2jaB13Xiw498tkD9 A X-Google-Smtp-Source: AGHT+IHcBazs1KoKTrZ3DdroHH04DM/SKr28uFu00SI0srezv50JszdEiHHXeKd4Hjq+Y6+ipXC1jw== X-Received: by 2002:a17:903:2307:b0:20b:9088:6545 with SMTP id d9443c01a7336-20bfe95dbcfmr96932395ad.46.1728141965422; Sat, 05 Oct 2024 08:26:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 13/20] target/arm: Pass MemOp to get_phys_addr Date: Sat, 5 Oct 2024 08:25:44 -0700 Message-ID: <20241005152551.307923-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1728142141721116600 Content-Type: text/plain; charset="utf-8" Zero is the safe do-nothing value for callers to use. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 3 ++- target/arm/ptw.c | 2 +- target/arm/tcg/m_helper.c | 8 ++++---- target/arm/tcg/tlb_helper.c | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1e5da81ce9..2b16579fa5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1432,6 +1432,7 @@ typedef struct GetPhysAddrResult { * @env: CPUARMState * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute + * @memop: memory operation feeding this access, or 0 for none * @mmu_idx: MMU index indicating required translation regime * @result: set on translation success. * @fi: set to fault info if the translation fails @@ -1450,7 +1451,7 @@ typedef struct GetPhysAddrResult { * value. */ bool get_phys_addr(CPUARMState *env, vaddr address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_i= dx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) __attribute__((nonnull)); =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 659855133c..373095a339 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3572,7 +3572,7 @@ bool get_phys_addr_with_space_nogpc(CPUARMState *env,= vaddr address, } =20 bool get_phys_addr(CPUARMState *env, vaddr address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_i= dx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { S1Translate ptw =3D { diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 23d7f73035..f7354f3c6e 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -222,7 +222,7 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr,= uint32_t value, int exc; bool exc_secure; =20 - if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_DATA_STORE, 0, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type =3D=3D ARMFault_QEMU_SFault) { if (mode =3D=3D STACK_LAZYFP) { @@ -311,7 +311,7 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest,= uint32_t addr, bool exc_secure; uint32_t value; =20 - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type =3D=3D ARMFault_QEMU_SFault) { qemu_log_mask(CPU_LOG_INT, @@ -2009,7 +2009,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, bool secure, "...really SecureFault with SFSR.INVEP\n"); return false; } - if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_INST_FETCH, 0, mmu_idx, &res, &fi)) { /* the MPU lookup failed */ env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_IACCVIOL_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secur= e); @@ -2045,7 +2045,7 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMM= UIdx mmu_idx, ARMMMUFaultInfo fi =3D {}; uint32_t value; =20 - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type =3D=3D ARMFault_QEMU_SFault) { qemu_log_mask(CPU_LOG_INT, diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 885bf4ec14..1d8b7bcaa2 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -344,7 +344,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, * return false. Otherwise populate fsr with ARM DFSR/IFSR fault * register format, and signal the fault. */ - ret =3D get_phys_addr(&cpu->env, address, access_type, + ret =3D get_phys_addr(&cpu->env, address, access_type, 0, core_to_arm_mmu_idx(&cpu->env, mmu_idx), &res, fi); if (likely(!ret)) { --=20 2.43.0