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Fri, 04 Oct 2024 09:34:54 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Thomas Huth , Richard Henderson , Pierrick Bouvier , qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 16/25] target/riscv: Use explicit little-endian LD/ST API Date: Fri, 4 Oct 2024 13:30:32 -0300 Message-ID: <20241004163042.85922-17-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241004163042.85922-1-philmd@linaro.org> References: <20241004163042.85922-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=philmd@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1728059916436116600 The Risc-V architecture uses little endianness. Directly use the little-endian LD/ST API. Mechanical change using: $ end=3Dle; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/riscv/); \ done Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/gdbstub.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index c07df972f1e..2e042f117f3 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -84,15 +84,15 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) =20 switch (mcc->misa_mxl_max) { case MXL_RV32: - tmp =3D (int32_t)ldl_p(mem_buf); + tmp =3D (int32_t)ldl_le_p(mem_buf); length =3D 4; break; case MXL_RV64: case MXL_RV128: if (env->xl < MXL_RV64) { - tmp =3D (int32_t)ldq_p(mem_buf); + tmp =3D (int32_t)ldq_le_p(mem_buf); } else { - tmp =3D ldq_p(mem_buf); + tmp =3D ldq_le_p(mem_buf); } length =3D 8; break; @@ -130,7 +130,7 @@ static int riscv_gdb_set_fpu(CPUState *cs, uint8_t *mem= _buf, int n) CPURISCVState *env =3D &cpu->env; =20 if (n < 32) { - env->fpr[n] =3D ldq_p(mem_buf); /* always 64-bit */ + env->fpr[n] =3D ldq_le_p(mem_buf); /* always 64-bit */ return sizeof(uint64_t); } return 0; @@ -162,7 +162,7 @@ static int riscv_gdb_set_vector(CPUState *cs, uint8_t *= mem_buf, int n) if (n < 32) { int i; for (i =3D 0; i < vlenb; i +=3D 8) { - env->vreg[(n * vlenb + i) / 8] =3D ldq_p(mem_buf + i); + env->vreg[(n * vlenb + i) / 8] =3D ldq_le_p(mem_buf + i); } return vlenb; } @@ -193,7 +193,7 @@ static int riscv_gdb_set_csr(CPUState *cs, uint8_t *mem= _buf, int n) CPURISCVState *env =3D &cpu->env; =20 if (n < CSR_TABLE_SIZE) { - target_ulong val =3D ldtul_p(mem_buf); + target_ulong val =3D ldtul_le_p(mem_buf); int result; =20 result =3D riscv_csrrw_debug(env, n, NULL, val, -1); @@ -226,7 +226,7 @@ static int riscv_gdb_set_virtual(CPUState *cs, uint8_t = *mem_buf, int n) RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; =20 - env->priv =3D ldtul_p(mem_buf) & 0x3; + env->priv =3D ldtul_le_p(mem_buf) & 0x3; if (env->priv =3D=3D PRV_RESERVED) { env->priv =3D PRV_S; } --=20 2.45.2