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Iglesias" , qemu-ppc@nongnu.org, Marcel Apfelbaum , Aleksandar Rikalo , Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Nicholas Piggin , qemu-arm@nongnu.org, Zhao Liu , Peter Maydell , Jiaxun Yang Subject: [PATCH 3/8] target/arm: Implement CPUClass::is_big_endian Date: Fri, 4 Oct 2024 13:21:13 -0300 Message-ID: <20241004162118.84570-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241004162118.84570-1-philmd@linaro.org> References: <20241004162118.84570-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=philmd@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1728058963545116600 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 19191c23918..2bb87a9299f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -122,6 +122,11 @@ void arm_restore_state_to_opc(CPUState *cs, } #endif /* CONFIG_TCG */ =20 +static bool arm_cpu_is_big_endian(CPUState *cs) +{ + return arm_cpu_data_is_big_endian(cpu_env(cs)); +} + /* * With SCTLR_ELx.NMI =3D=3D 0, IRQ with Superpriority is masked identical= ly with * IRQ without Superpriority. Moreover, if the GIC is configured so that @@ -2692,6 +2697,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) &acc->parent_phases); =20 cc->class_by_name =3D arm_cpu_class_by_name; + cc->is_big_endian =3D arm_cpu_is_big_endian; cc->has_work =3D arm_cpu_has_work; cc->mmu_index =3D arm_cpu_mmu_index; cc->dump_state =3D arm_cpu_dump_state; --=20 2.45.2