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[200.206.229.93]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c139306cfsm107635ad.170.2024.10.04.08.57.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 08:57:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1728057480; x=1728662280; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BV4yX6u78pLPUdOBk5Pji6b+eM9Z4jojvmboMcWYuOA=; b=DYB6MCQ5hBz09AfjQm5NRUhnp5dos7b/9GegvuaWxsECLS1rsCvhRER19LdIz6bZKu oQ7VTHRSHI7anUo3GocPZeH5tiHrUNDe+3o8ClBHqEz7Q0/W5uZfrcggZAQxJnLnB+dn uE8OruAYjPgtSFzaxdoClA/Sktw9ncIMORuCL2LtbAVL9Nt56blt4cMDJnnTtjSKLx1n Pt0yRChAD8DfZYpEsA1u5Lf8mFYkCYRyOpl65n7TdQr4wa9f8fo4Nm4Iev/7OsFqhpMe /fNq4qfXr/eBteB+V2dSQGEH8H9B27zn+wAbQ9Ww7tmU4u7Tc66sjE0xSaq+gfWQe52X vPQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728057480; x=1728662280; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BV4yX6u78pLPUdOBk5Pji6b+eM9Z4jojvmboMcWYuOA=; b=q456XrPH+7H8GLvaulYqCA5OycrQN3fnRy1iI7dBJeb0kLbhhyBSIKN8SeiwWvEBO6 g916D28ixFjY0JJjQDKIXO+hUoQ9UKH0/yUSgaIGqkbK/QNO5BpMDPQCgq5GPxCvZ05g 3zwzCH8XV6BAg3IBblw6N22bdQCulKWb4VwyQr+NNOlstS9Z71jMShOnhyFsQ/ybbwKi kbklZEqrq+2MAYf4CGoYzkF391U1UjZ45Qw9negHmnR56usP88OjAGkAJ+hND2GFM99+ iAvrY+bZFgNlGxPSVLE6HfIs91hxbHINm2657/eOzg4gKexPa057NXKJ32KIJeN+TVQA 1Krw== X-Gm-Message-State: AOJu0YylSFM4QPlS5KCrZmYFlyhWb10FO/5CUUFBqc6MwRpuyH4lJaww I2Bj3ddakeufOZeHh+lwyeHwyWHmbFinSUSH7deZg8s1sZ0tMmiFHsY0wPbkuh4DdkgG9ivv90l T X-Google-Smtp-Source: AGHT+IEX8qr5/wbLS9SYyG7cC93orGEZvRVMAKqnsAnNQnNW5r7Dbip+dML4siWJeK6v63bYXPGzqg== X-Received: by 2002:a05:6a21:3a81:b0:1d5:2f56:9fe5 with SMTP id adf61e73a8af0-1d6dfac81dfmr4444335637.39.1728057479679; Fri, 04 Oct 2024 08:57:59 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Tomasz Jeznach , Daniel Henrique Barboza , Frank Chang Subject: [PATCH v9 09/12] hw/riscv/riscv-iommu: add ATS support Date: Fri, 4 Oct 2024 12:57:16 -0300 Message-ID: <20241004155721.2154626-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241004155721.2154626-1-dbarboza@ventanamicro.com> References: <20241004155721.2154626-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1728057515554116600 Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach Add PCIe Address Translation Services (ATS) capabilities to the IOMMU. This will add support for ATS translation requests in Fault/Event queues, Page-request queue and IOATC invalidations. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Acked-by: Alistair Francis --- hw/riscv/riscv-iommu-bits.h | 43 +++++++++++- hw/riscv/riscv-iommu.c | 127 +++++++++++++++++++++++++++++++++++- hw/riscv/riscv-iommu.h | 1 + hw/riscv/trace-events | 3 + 4 files changed, 171 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h index b1c477f5c3..96a994b9aa 100644 --- a/hw/riscv/riscv-iommu-bits.h +++ b/hw/riscv/riscv-iommu-bits.h @@ -79,6 +79,7 @@ struct riscv_iommu_pq_record { #define RISCV_IOMMU_CAP_SV57X4 BIT_ULL(19) #define RISCV_IOMMU_CAP_MSI_FLAT BIT_ULL(22) #define RISCV_IOMMU_CAP_MSI_MRIF BIT_ULL(23) +#define RISCV_IOMMU_CAP_ATS BIT_ULL(25) #define RISCV_IOMMU_CAP_T2GPA BIT_ULL(26) #define RISCV_IOMMU_CAP_IGS GENMASK_ULL(29, 28) #define RISCV_IOMMU_CAP_PAS GENMASK_ULL(37, 32) @@ -212,6 +213,7 @@ struct riscv_iommu_dc { =20 /* Translation control fields */ #define RISCV_IOMMU_DC_TC_V BIT_ULL(0) +#define RISCV_IOMMU_DC_TC_EN_ATS BIT_ULL(1) #define RISCV_IOMMU_DC_TC_EN_PRI BIT_ULL(2) #define RISCV_IOMMU_DC_TC_T2GPA BIT_ULL(3) #define RISCV_IOMMU_DC_TC_DTF BIT_ULL(4) @@ -273,6 +275,20 @@ struct riscv_iommu_command { #define RISCV_IOMMU_CMD_IODIR_DV BIT_ULL(33) #define RISCV_IOMMU_CMD_IODIR_DID GENMASK_ULL(63, 40) =20 +/* 3.1.4 I/O MMU PCIe ATS */ +#define RISCV_IOMMU_CMD_ATS_OPCODE 4 +#define RISCV_IOMMU_CMD_ATS_FUNC_INVAL 0 +#define RISCV_IOMMU_CMD_ATS_FUNC_PRGR 1 +#define RISCV_IOMMU_CMD_ATS_PID GENMASK_ULL(31, 12) +#define RISCV_IOMMU_CMD_ATS_PV BIT_ULL(32) +#define RISCV_IOMMU_CMD_ATS_DSV BIT_ULL(33) +#define RISCV_IOMMU_CMD_ATS_RID GENMASK_ULL(55, 40) +#define RISCV_IOMMU_CMD_ATS_DSEG GENMASK_ULL(63, 56) +/* dword1 is the ATS payload, two different payload types for INVAL and PR= GR */ + +/* ATS.PRGR payload */ +#define RISCV_IOMMU_CMD_ATS_PRGR_RESP_CODE GENMASK_ULL(47, 44) + enum riscv_iommu_dc_fsc_atp_modes { RISCV_IOMMU_DC_FSC_MODE_BARE =3D 0, RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32 =3D 8, @@ -339,7 +355,32 @@ enum riscv_iommu_fq_ttypes { RISCV_IOMMU_FQ_TTYPE_TADDR_INST_FETCH =3D 5, RISCV_IOMMU_FQ_TTYPE_TADDR_RD =3D 6, RISCV_IOMMU_FQ_TTYPE_TADDR_WR =3D 7, - RISCV_IOMMU_FW_TTYPE_PCIE_MSG_REQ =3D 8, + RISCV_IOMMU_FQ_TTYPE_PCIE_ATS_REQ =3D 8, + RISCV_IOMMU_FW_TTYPE_PCIE_MSG_REQ =3D 9, +}; + +/* Header fields */ +#define RISCV_IOMMU_PREQ_HDR_PID GENMASK_ULL(31, 12) +#define RISCV_IOMMU_PREQ_HDR_PV BIT_ULL(32) +#define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33) +#define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34) +#define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40) + +/* Payload fields */ +#define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0) +#define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1) +#define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2) +#define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0) +#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3) +#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12) + + +/* + * struct riscv_iommu_msi_pte - MSI Page Table Entry + */ +struct riscv_iommu_msi_pte { + uint64_t pte; + uint64_t mrif_info; }; =20 /* Fields on pte */ diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index cef54b56ba..5d7bbd78c7 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -669,6 +669,20 @@ static bool riscv_iommu_validate_device_ctx(RISCVIOMMU= State *s, RISCVIOMMUContext *ctx) { uint32_t fsc_mode, msi_mode; + uint64_t gatp; + + if (!(s->cap & RISCV_IOMMU_CAP_ATS) && + (ctx->tc & RISCV_IOMMU_DC_TC_EN_ATS || + ctx->tc & RISCV_IOMMU_DC_TC_EN_PRI || + ctx->tc & RISCV_IOMMU_DC_TC_PRPR)) { + return false; + } + + if (!(ctx->tc & RISCV_IOMMU_DC_TC_EN_ATS) && + (ctx->tc & RISCV_IOMMU_DC_TC_T2GPA || + ctx->tc & RISCV_IOMMU_DC_TC_EN_PRI)) { + return false; + } =20 if (!(ctx->tc & RISCV_IOMMU_DC_TC_EN_PRI) && ctx->tc & RISCV_IOMMU_DC_TC_PRPR) { @@ -689,6 +703,12 @@ static bool riscv_iommu_validate_device_ctx(RISCVIOMMU= State *s, } } =20 + gatp =3D get_field(ctx->gatp, RISCV_IOMMU_ATP_MODE_FIELD); + if (ctx->tc & RISCV_IOMMU_DC_TC_T2GPA && + gatp =3D=3D RISCV_IOMMU_DC_IOHGATP_MODE_BARE) { + return false; + } + fsc_mode =3D get_field(ctx->satp, RISCV_IOMMU_DC_FSC_MODE); =20 if (ctx->tc & RISCV_IOMMU_DC_TC_PDTV) { @@ -839,7 +859,12 @@ static int riscv_iommu_ctx_fetch(RISCVIOMMUState *s, R= ISCVIOMMUContext *ctx) RISCV_IOMMU_DC_IOHGATP_MODE_BARE); ctx->satp =3D set_field(0, RISCV_IOMMU_ATP_MODE_FIELD, RISCV_IOMMU_DC_FSC_MODE_BARE); + ctx->tc =3D RISCV_IOMMU_DC_TC_V; + if (s->enable_ats) { + ctx->tc |=3D RISCV_IOMMU_DC_TC_EN_ATS; + } + ctx->ta =3D 0; ctx->msiptp =3D 0; return 0; @@ -1296,6 +1321,16 @@ static int riscv_iommu_translate(RISCVIOMMUState *s,= RISCVIOMMUContext *ctx, enable_pri =3D (iotlb->perm =3D=3D IOMMU_NONE) && (ctx->tc & BIT_ULL(3= 2)); enable_pid =3D (ctx->tc & RISCV_IOMMU_DC_TC_PDTV); =20 + /* Check for ATS request. */ + if (iotlb->perm =3D=3D IOMMU_NONE) { + /* Check if ATS is disabled. */ + if (!(ctx->tc & RISCV_IOMMU_DC_TC_EN_ATS)) { + enable_pri =3D false; + fault =3D RISCV_IOMMU_FQ_CAUSE_TTYPE_BLOCKED; + goto done; + } + } + iot =3D riscv_iommu_iot_lookup(ctx, iot_cache, iotlb->iova); perm =3D iot ? iot->perm : IOMMU_NONE; if (perm !=3D IOMMU_NONE) { @@ -1347,11 +1382,11 @@ done: } =20 if (fault) { - unsigned ttype; + unsigned ttype =3D RISCV_IOMMU_FQ_TTYPE_PCIE_ATS_REQ; =20 if (iotlb->perm & IOMMU_RW) { ttype =3D RISCV_IOMMU_FQ_TTYPE_UADDR_WR; - } else { + } else if (iotlb->perm & IOMMU_RO) { ttype =3D RISCV_IOMMU_FQ_TTYPE_UADDR_RD; } =20 @@ -1379,6 +1414,71 @@ static MemTxResult riscv_iommu_iofence(RISCVIOMMUSta= te *s, bool notify, MEMTXATTRS_UNSPECIFIED); } =20 +static void riscv_iommu_ats(RISCVIOMMUState *s, + struct riscv_iommu_command *cmd, IOMMUNotifierFlag flag, + IOMMUAccessFlags perm, + void (*trace_fn)(const char *id)) +{ + RISCVIOMMUSpace *as =3D NULL; + IOMMUNotifier *n; + IOMMUTLBEvent event; + uint32_t pid; + uint32_t devid; + const bool pv =3D cmd->dword0 & RISCV_IOMMU_CMD_ATS_PV; + + if (cmd->dword0 & RISCV_IOMMU_CMD_ATS_DSV) { + /* Use device segment and requester id */ + devid =3D get_field(cmd->dword0, + RISCV_IOMMU_CMD_ATS_DSEG | RISCV_IOMMU_CMD_ATS_RID); + } else { + devid =3D get_field(cmd->dword0, RISCV_IOMMU_CMD_ATS_RID); + } + + pid =3D get_field(cmd->dword0, RISCV_IOMMU_CMD_ATS_PID); + + QLIST_FOREACH(as, &s->spaces, list) { + if (as->devid =3D=3D devid) { + break; + } + } + + if (!as || !as->notifier) { + return; + } + + event.type =3D flag; + event.entry.perm =3D perm; + event.entry.target_as =3D s->target_as; + + IOMMU_NOTIFIER_FOREACH(n, &as->iova_mr) { + if (!pv || n->iommu_idx =3D=3D pid) { + event.entry.iova =3D n->start; + event.entry.addr_mask =3D n->end - n->start; + trace_fn(as->iova_mr.parent_obj.name); + memory_region_notify_iommu_one(n, &event); + } + } +} + +static void riscv_iommu_ats_inval(RISCVIOMMUState *s, + struct riscv_iommu_command *cmd) +{ + return riscv_iommu_ats(s, cmd, IOMMU_NOTIFIER_DEVIOTLB_UNMAP, IOMMU_NO= NE, + trace_riscv_iommu_ats_inval); +} + +static void riscv_iommu_ats_prgr(RISCVIOMMUState *s, + struct riscv_iommu_command *cmd) +{ + unsigned resp_code =3D get_field(cmd->dword1, + RISCV_IOMMU_CMD_ATS_PRGR_RESP_CODE); + + /* Using the access flag to carry response code information */ + IOMMUAccessFlags perm =3D resp_code ? IOMMU_NONE : IOMMU_RW; + return riscv_iommu_ats(s, cmd, IOMMU_NOTIFIER_MAP, perm, + trace_riscv_iommu_ats_prgr); +} + static void riscv_iommu_process_ddtp(RISCVIOMMUState *s) { uint64_t old_ddtp =3D s->ddtp; @@ -1534,6 +1634,25 @@ static void riscv_iommu_process_cq_tail(RISCVIOMMUSt= ate *s) get_field(cmd.dword0, RISCV_IOMMU_CMD_IODIR_PID)); break; =20 + /* ATS commands */ + case RISCV_IOMMU_CMD(RISCV_IOMMU_CMD_ATS_FUNC_INVAL, + RISCV_IOMMU_CMD_ATS_OPCODE): + if (!s->enable_ats) { + goto cmd_ill; + } + + riscv_iommu_ats_inval(s, &cmd); + break; + + case RISCV_IOMMU_CMD(RISCV_IOMMU_CMD_ATS_FUNC_PRGR, + RISCV_IOMMU_CMD_ATS_OPCODE): + if (!s->enable_ats) { + goto cmd_ill; + } + + riscv_iommu_ats_prgr(s, &cmd); + break; + default: cmd_ill: /* Invalid instruction, do not advance instruction index. */ @@ -1935,6 +2054,9 @@ static void riscv_iommu_realize(DeviceState *dev, Err= or **errp) if (s->enable_msi) { s->cap |=3D RISCV_IOMMU_CAP_MSI_FLAT | RISCV_IOMMU_CAP_MSI_MRIF; } + if (s->enable_ats) { + s->cap |=3D RISCV_IOMMU_CAP_ATS; + } if (s->enable_s_stage) { s->cap |=3D RISCV_IOMMU_CAP_SV32 | RISCV_IOMMU_CAP_SV39 | RISCV_IOMMU_CAP_SV48 | RISCV_IOMMU_CAP_SV57; @@ -2044,6 +2166,7 @@ static Property riscv_iommu_properties[] =3D { DEFINE_PROP_UINT32("ioatc-limit", RISCVIOMMUState, iot_limit, LIMIT_CACHE_IOT), DEFINE_PROP_BOOL("intremap", RISCVIOMMUState, enable_msi, TRUE), + DEFINE_PROP_BOOL("ats", RISCVIOMMUState, enable_ats, TRUE), DEFINE_PROP_BOOL("off", RISCVIOMMUState, enable_off, TRUE), DEFINE_PROP_BOOL("s-stage", RISCVIOMMUState, enable_s_stage, TRUE), DEFINE_PROP_BOOL("g-stage", RISCVIOMMUState, enable_g_stage, TRUE), diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h index 9f15f3b27f..da3f03440c 100644 --- a/hw/riscv/riscv-iommu.h +++ b/hw/riscv/riscv-iommu.h @@ -37,6 +37,7 @@ struct RISCVIOMMUState { =20 bool enable_off; /* Enable out-of-reset OFF mode (DMA disabled) */ bool enable_msi; /* Enable MSI remapping */ + bool enable_ats; /* Enable ATS support */ bool enable_s_stage; /* Enable S/VS-Stage translation */ bool enable_g_stage; /* Enable G-Stage translation */ =20 diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events index 3d5c33102d..0527c56c91 100644 --- a/hw/riscv/trace-events +++ b/hw/riscv/trace-events @@ -12,3 +12,6 @@ riscv_iommu_notifier_add(const char *id) "%s: dev-iotlb n= otifier added" riscv_iommu_notifier_del(const char *id) "%s: dev-iotlb notifier removed" riscv_iommu_notify_int_vector(uint32_t cause, uint32_t vector) "Interrupt = cause 0x%x sent via vector 0x%x" riscv_iommu_icvec_write(uint32_t orig, uint32_t actual) "ICVEC write: inco= ming 0x%x actual 0x%x" +riscv_iommu_ats(const char *id, unsigned b, unsigned d, unsigned f, uint64= _t iova) "%s: translate request %04x:%02x.%u iova: 0x%"PRIx64 +riscv_iommu_ats_inval(const char *id) "%s: dev-iotlb invalidate" +riscv_iommu_ats_prgr(const char *id) "%s: dev-iotlb page request group res= ponse" --=20 2.45.2