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Tsirkin" , Thomas Huth , Bastian Koppelmann , Richard Henderson , Pierrick Bouvier Subject: [PATCH 08/16] hw/ppc/e500: Use explicit big-endian LD/ST API Date: Fri, 4 Oct 2024 01:42:03 +0200 Message-ID: <20241003234211.53644-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241003234211.53644-1-philmd@linaro.org> References: <20241003234211.53644-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727999073079116600 The 32-bit PPC architecture uses big endianness. Directly use the big-endian LD/ST API for the E500 hardware. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/ppc/ppce500_spin.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index e08739a443d..8e0ef9467e4 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -64,9 +64,9 @@ static void spin_reset(DeviceState *dev) for (i =3D 0; i < MAX_CPUS; i++) { SpinInfo *info =3D &s->spin[i]; =20 - stl_p(&info->pir, i); - stq_p(&info->r3, i); - stq_p(&info->addr, 1); + stl_be_p(&info->pir, i); + stq_be_p(&info->r3, i); + stq_be_p(&info->addr, 1); } } =20 @@ -96,9 +96,9 @@ static void spin_kick(CPUState *cs, run_on_cpu_data data) hwaddr map_start; =20 cpu_synchronize_state(cs); - stl_p(&curspin->pir, env->spr[SPR_BOOKE_PIR]); - env->nip =3D ldq_p(&curspin->addr) & (map_size - 1); - env->gpr[3] =3D ldq_p(&curspin->r3); + stl_be_p(&curspin->pir, env->spr[SPR_BOOKE_PIR]); + env->nip =3D ldq_be_p(&curspin->addr) & (map_size - 1); + env->gpr[3] =3D ldq_be_p(&curspin->r3); env->gpr[4] =3D 0; env->gpr[5] =3D 0; env->gpr[6] =3D 0; @@ -106,7 +106,7 @@ static void spin_kick(CPUState *cs, run_on_cpu_data dat= a) env->gpr[8] =3D 0; env->gpr[9] =3D 0; =20 - map_start =3D ldq_p(&curspin->addr) & ~(map_size - 1); + map_start =3D ldq_be_p(&curspin->addr) & ~(map_size - 1); mmubooke_create_initial_mapping(env, 0, map_start, map_size); =20 cs->halted =3D 0; @@ -141,14 +141,14 @@ static void spin_write(void *opaque, hwaddr addr, uin= t64_t value, stb_p(curspin_p, value); break; case 2: - stw_p(curspin_p, value); + stw_be_p(curspin_p, value); break; case 4: - stl_p(curspin_p, value); + stl_be_p(curspin_p, value); break; } =20 - if (!(ldq_p(&curspin->addr) & 1)) { + if (!(ldq_be_p(&curspin->addr) & 1)) { /* run CPU */ run_on_cpu(cpu, spin_kick, RUN_ON_CPU_HOST_PTR(curspin)); } @@ -163,9 +163,9 @@ static uint64_t spin_read(void *opaque, hwaddr addr, un= signed len) case 1: return ldub_p(spin_p); case 2: - return lduw_p(spin_p); + return lduw_be_p(spin_p); case 4: - return ldl_p(spin_p); + return ldl_be_p(spin_p); default: hw_error("ppce500: unexpected %s with len =3D %u", __func__, len); } --=20 2.45.2