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Tsirkin" , Thomas Huth , Bastian Koppelmann , Richard Henderson , Pierrick Bouvier Subject: [PATCH 05/16] target/i386: Use explicit little-endian LD/ST API Date: Fri, 4 Oct 2024 01:42:00 +0200 Message-ID: <20241003234211.53644-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241003234211.53644-1-philmd@linaro.org> References: <20241003234211.53644-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727999095183116600 The x86 architecture uses little endianness. Directly use the little-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/gdbstub.c | 26 +++++++++++----------- target/i386/tcg/sysemu/excp_helper.c | 4 ++-- target/i386/xsave_helper.c | 32 ++++++++++++++-------------- 3 files changed, 31 insertions(+), 31 deletions(-) diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index 4acf485879e..40c8cb6dc46 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -89,10 +89,10 @@ static int gdb_read_reg_cs64(uint32_t hflags, GByteArra= y *buf, target_ulong val) static int gdb_write_reg_cs64(uint32_t hflags, uint8_t *buf, target_ulong = *val) { if (hflags & HF_CS64_MASK) { - *val =3D ldq_p(buf); + *val =3D ldq_le_p(buf); return 8; } - *val =3D ldl_p(buf); + *val =3D ldl_le_p(buf); return 4; } =20 @@ -221,7 +221,7 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) static int x86_cpu_gdb_load_seg(X86CPU *cpu, X86Seg sreg, uint8_t *mem_buf) { CPUX86State *env =3D &cpu->env; - uint16_t selector =3D ldl_p(mem_buf); + uint16_t selector =3D ldl_le_p(mem_buf); =20 if (selector !=3D env->segs[sreg].selector) { #if defined(CONFIG_USER_ONLY) @@ -270,7 +270,7 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) } else if (n < CPU_NB_REGS32) { n =3D gpr_map32[n]; env->regs[n] &=3D ~0xffffffffUL; - env->regs[n] |=3D (uint32_t)ldl_p(mem_buf); + env->regs[n] |=3D (uint32_t)ldl_le_p(mem_buf); return 4; } } else if (n >=3D IDX_FP_REGS && n < IDX_FP_REGS + 8) { @@ -281,8 +281,8 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) } else if (n >=3D IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { n -=3D IDX_XMM_REGS; if (n < CPU_NB_REGS32 || TARGET_LONG_BITS =3D=3D 64) { - env->xmm_regs[n].ZMM_Q(0) =3D ldq_p(mem_buf); - env->xmm_regs[n].ZMM_Q(1) =3D ldq_p(mem_buf + 8); + env->xmm_regs[n].ZMM_Q(0) =3D ldq_le_p(mem_buf); + env->xmm_regs[n].ZMM_Q(1) =3D ldq_le_p(mem_buf + 8); return 16; } } else { @@ -290,18 +290,18 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) case IDX_IP_REG: if (TARGET_LONG_BITS =3D=3D 64) { if (env->hflags & HF_CS64_MASK) { - env->eip =3D ldq_p(mem_buf); + env->eip =3D ldq_le_p(mem_buf); } else { - env->eip =3D ldq_p(mem_buf) & 0xffffffffUL; + env->eip =3D ldq_le_p(mem_buf) & 0xffffffffUL; } return 8; } else { env->eip &=3D ~0xffffffffUL; - env->eip |=3D (uint32_t)ldl_p(mem_buf); + env->eip |=3D (uint32_t)ldl_le_p(mem_buf); return 4; } case IDX_FLAGS_REG: - env->eflags =3D ldl_p(mem_buf); + env->eflags =3D ldl_le_p(mem_buf); return 4; =20 case IDX_SEG_REGS: @@ -327,10 +327,10 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) return 4; =20 case IDX_FP_REGS + 8: - cpu_set_fpuc(env, ldl_p(mem_buf)); + cpu_set_fpuc(env, ldl_le_p(mem_buf)); return 4; case IDX_FP_REGS + 9: - tmp =3D ldl_p(mem_buf); + tmp =3D ldl_le_p(mem_buf); env->fpstt =3D (tmp >> 11) & 7; env->fpus =3D tmp & ~0x3800; return 4; @@ -348,7 +348,7 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) return 4; =20 case IDX_MXCSR_REG: - cpu_set_mxcsr(env, ldl_p(mem_buf)); + cpu_set_mxcsr(env, ldl_le_p(mem_buf)); return 4; =20 case IDX_CTL_CR0_REG: diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 8fb05b1f531..de6765099f3 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -86,7 +86,7 @@ static bool ptw_translate(PTETranslate *inout, hwaddr add= r, uint64_t ra) static inline uint32_t ptw_ldl(const PTETranslate *in, uint64_t ra) { if (likely(in->haddr)) { - return ldl_p(in->haddr); + return ldl_le_p(in->haddr); } return cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); } @@ -94,7 +94,7 @@ static inline uint32_t ptw_ldl(const PTETranslate *in, ui= nt64_t ra) static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra) { if (likely(in->haddr)) { - return ldq_p(in->haddr); + return ldq_le_p(in->haddr); } return cpu_ldq_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); } diff --git a/target/i386/xsave_helper.c b/target/i386/xsave_helper.c index 996e9f3bfef..fc10bfa6718 100644 --- a/target/i386/xsave_helper.c +++ b/target/i386/xsave_helper.c @@ -43,8 +43,8 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint= 32_t buflen) for (i =3D 0; i < CPU_NB_REGS; i++) { uint8_t *xmm =3D legacy->xmm_regs[i]; =20 - stq_p(xmm, env->xmm_regs[i].ZMM_Q(0)); - stq_p(xmm + 8, env->xmm_regs[i].ZMM_Q(1)); + stq_le_p(xmm, env->xmm_regs[i].ZMM_Q(0)); + stq_le_p(xmm + 8, env->xmm_regs[i].ZMM_Q(1)); } =20 header->xstate_bv =3D env->xstate_bv; @@ -58,8 +58,8 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint= 32_t buflen) for (i =3D 0; i < CPU_NB_REGS; i++) { uint8_t *ymmh =3D avx->ymmh[i]; =20 - stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2)); - stq_p(ymmh + 8, env->xmm_regs[i].ZMM_Q(3)); + stq_le_p(ymmh, env->xmm_regs[i].ZMM_Q(2)); + stq_le_p(ymmh + 8, env->xmm_regs[i].ZMM_Q(3)); } } =20 @@ -101,10 +101,10 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, = uint32_t buflen) for (i =3D 0; i < CPU_NB_REGS; i++) { uint8_t *zmmh =3D zmm_hi256->zmm_hi256[i]; =20 - stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4)); - stq_p(zmmh + 8, env->xmm_regs[i].ZMM_Q(5)); - stq_p(zmmh + 16, env->xmm_regs[i].ZMM_Q(6)); - stq_p(zmmh + 24, env->xmm_regs[i].ZMM_Q(7)); + stq_le_p(zmmh, env->xmm_regs[i].ZMM_Q(4)); + stq_le_p(zmmh + 8, env->xmm_regs[i].ZMM_Q(5)); + stq_le_p(zmmh + 16, env->xmm_regs[i].ZMM_Q(6)); + stq_le_p(zmmh + 24, env->xmm_regs[i].ZMM_Q(7)); } =20 #ifdef TARGET_X86_64 @@ -177,8 +177,8 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *= buf, uint32_t buflen) for (i =3D 0; i < CPU_NB_REGS; i++) { const uint8_t *xmm =3D legacy->xmm_regs[i]; =20 - env->xmm_regs[i].ZMM_Q(0) =3D ldq_p(xmm); - env->xmm_regs[i].ZMM_Q(1) =3D ldq_p(xmm + 8); + env->xmm_regs[i].ZMM_Q(0) =3D ldq_le_p(xmm); + env->xmm_regs[i].ZMM_Q(1) =3D ldq_le_p(xmm + 8); } =20 env->xstate_bv =3D header->xstate_bv; @@ -191,8 +191,8 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *= buf, uint32_t buflen) for (i =3D 0; i < CPU_NB_REGS; i++) { const uint8_t *ymmh =3D avx->ymmh[i]; =20 - env->xmm_regs[i].ZMM_Q(2) =3D ldq_p(ymmh); - env->xmm_regs[i].ZMM_Q(3) =3D ldq_p(ymmh + 8); + env->xmm_regs[i].ZMM_Q(2) =3D ldq_le_p(ymmh); + env->xmm_regs[i].ZMM_Q(3) =3D ldq_le_p(ymmh + 8); } } =20 @@ -241,10 +241,10 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void= *buf, uint32_t buflen) for (i =3D 0; i < CPU_NB_REGS; i++) { const uint8_t *zmmh =3D zmm_hi256->zmm_hi256[i]; =20 - env->xmm_regs[i].ZMM_Q(4) =3D ldq_p(zmmh); - env->xmm_regs[i].ZMM_Q(5) =3D ldq_p(zmmh + 8); - env->xmm_regs[i].ZMM_Q(6) =3D ldq_p(zmmh + 16); - env->xmm_regs[i].ZMM_Q(7) =3D ldq_p(zmmh + 24); + env->xmm_regs[i].ZMM_Q(4) =3D ldq_le_p(zmmh); + env->xmm_regs[i].ZMM_Q(5) =3D ldq_le_p(zmmh + 8); + env->xmm_regs[i].ZMM_Q(6) =3D ldq_le_p(zmmh + 16); + env->xmm_regs[i].ZMM_Q(7) =3D ldq_le_p(zmmh + 24); } =20 #ifdef TARGET_X86_64 --=20 2.45.2