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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20b37e60c76sm78324235ad.269.2024.10.01.22.51.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2024 22:51:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1727848280; x=1728453080; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3EI0kHcPUo6x2eDcs+2KIC40XgBNh/atV1LPebowvuc=; b=IKmB27JSDaqpGHNMkV4VF71HMt//IxEKMKbkqb74cTKPqvN+WNJ1cIl5kLW2htkcUM UMh7VksYr3P8s+BL7e9GQMcU4A5ysE5hQEYau53KrCaR5rjyIx9Xtxbnr21yntGLNqZp obWFfKZQkEzoN9t5qS3kezHkLaRQPEQFLxxtaijcDm3s14tSUqI4n7TiBP4yOvSnsY8t nzlNEa6xMjIXGNKGw1Hq/WjuwC0kwN/LLuPmtjgnLwgKNUTY1wp8A1Dg4tgGWGJVsmfd yOTREC7IIwB9EiJRfLhRa0/Cf8eAnIOsUM/Jbo//sn4pWqpW1tgDGc08las8MBvNuyyK pnWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727848280; x=1728453080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3EI0kHcPUo6x2eDcs+2KIC40XgBNh/atV1LPebowvuc=; b=MZZiK31NFGaVc+/4wPWrcyQsZGxwL2D68oy7bqEAgWT9WQxTHCyWa8yMjG6KK+18Nz n3bC6Y7jZnXBR0NMDlgexb+5tvRXno/wROVQpBCsCLDlXtpN+qu8WQcIjMb8dW0tBlDs KEgX5A6QMiPUyaY777AEPzyFuTVXLamb+mkEx42LrPv+6KO7pqYDJ31odRf0jubLZDaR nQ55b2mUBTLPn1d1vUgNth9DyqLa7QvvAUBFEwbFZ3IoJe4LI7nsxPjPShn/BWxLyiIG Eb111JqSHy/BVZwhQoK92c2t1bW2EiAx/1+M2OsB2rzL23i4ne8ZlmWbPxbg5yWSoqJV X/Bw== X-Gm-Message-State: AOJu0Ywbj59iWdrM/C8U9g3vZP6XaXFK+Jz/OZEfRxY4Catg00MIc8RW pYPpZWrrEeJJPvWzVdNE6oXvtqGTt9MQD63Ms5etf1x5sOjiIS0AkuOLA4L9 X-Google-Smtp-Source: AGHT+IGE0j1kMdboAeZwtGhDlYUMfgr+B4vNiOFZCauuscRDmdIeYKkvGqNjcsgE9liJIWFAWitTdg== X-Received: by 2002:a17:902:da8e:b0:20b:9062:7b08 with SMTP id d9443c01a7336-20bc5a94f9dmr31384235ad.45.1727848280068; Tue, 01 Oct 2024 22:51:20 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alistair Francis , Daniel Henrique Barboza Subject: [PULL v3 07/35] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU Date: Wed, 2 Oct 2024 15:50:20 +1000 Message-ID: <20241002055048.556083-8-alistair.francis@wdc.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241002055048.556083-1-alistair.francis@wdc.com> References: <20241002055048.556083-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1727848498783116600 Content-Type: text/plain; charset="utf-8" From: Alistair Francis The OpenTitan Ibex CPU now supports the the Zba, Zbb, Zbc and Zbs bit-manipulation sub-extensions ratified in v.1.0.0 of the RISC-V Bit- Manipulation ISA Extension, so let's enable them in QEMU as well. 1: https://github.com/lowRISC/opentitan/pull/9748 Signed-off-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20240823003231.3522113-1-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0f8189bcf0..a1ca12077f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -680,6 +680,11 @@ static void rv32_ibex_cpu_init(Object *obj) cpu->cfg.ext_zicsr =3D true; cpu->cfg.pmp =3D true; cpu->cfg.ext_smepmp =3D true; + + cpu->cfg.ext_zba =3D true; + cpu->cfg.ext_zbb =3D true; + cpu->cfg.ext_zbc =3D true; + cpu->cfg.ext_zbs =3D true; } =20 static void rv32_imafcu_nommu_cpu_init(Object *obj) --=20 2.46.2