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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20b37e60c76sm78324235ad.269.2024.10.01.22.52.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2024 22:52:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1727848325; x=1728453125; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E9q8o1rqxr0ztdJ6JFR1Lgtcsz6qa9Ata3gYfSSUHnU=; b=jJmwI6yARVEuscCMhaRbCrI/jl6vFSEbnqrdaa0XJLjCCmilvD3N4lgQWbytoAWArH ZaWAb7jyigyPZPJ2MsCm8Xu+rRQFEAv3GpyuvI7vxi3LWgqag/XHcIfV2dfR4Zk49WUH yf2IZO0ORDvzneEqQ7DwXoSyxggQEjO4yGFwugNzgdvsLaKibr7kqpb5zBBQjpNk7Z1m ii2aN5f3AnhOT0sTZ+ef1HDVp8a2719xrmaa0YQjKCFNxzvEkgB5zixvEFM3+wRXGTwd yoCJtzCpUuFkShPTYjXvxTISSpxOKEHmXFNwjxVNDxURCbVWNMfiKYpfJIWYVrrDsp29 FI6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727848325; x=1728453125; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E9q8o1rqxr0ztdJ6JFR1Lgtcsz6qa9Ata3gYfSSUHnU=; b=KpjInLtCDZU1Wq07ZJa8Mcrf33X1EFPTRwcXkrrHCC8j9QbzwpY4Hc1DjyiLbg7EWl moVZ2isFrJYROykbYG6bOOg+tsg+6Cc+mvjMBb1MgxWFC5xp9wue3abnTJWNSkkwf9sh p4e0zd8rDVG99bnkCY2KANSxDJoS7za7x1JjJO3wN8jcfFN9OJAoo9L2Jzrgg9wdyKcx 6E+IIDZdCKBVJeLkft760Pj3xG5Ix7hEtBa6iuH/WblFuRllq5OEIrvxHbF0BGh2V7jJ aVaNN8nchASLTYCF7Qwvg9GXmk4lPFor8rZKlqtLKFFDagN7z1B9HgCLACuN0S52qjLK xY8A== X-Gm-Message-State: AOJu0YxWT0k3Eptd6nF1DmSw2jymg+lZ5AVztRBUzCvbrD6rRb8CFkO1 erva6L0bI6GJ9xxGXkD4seUWiksyp065fsrZV7tYHZEtd5GUdv8INPkfaIOe X-Google-Smtp-Source: AGHT+IFCbG3QMi8BMfBp88QxxixZ1Desvk/ExKDaLrpb6EgRcmiGobHgwTROCDnLZFrEQpDlRhhUHQ== X-Received: by 2002:a17:902:da8f:b0:20b:5231:cd61 with SMTP id d9443c01a7336-20bc5a20b08mr29326885ad.24.1727848324947; Tue, 01 Oct 2024 22:52:04 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Mark Corbin , Ajeet Singh , Richard Henderson , Alistair Francis Subject: [PULL v3 22/35] bsd-user: Implement RISC-V TLS register setup Date: Wed, 2 Oct 2024 15:50:35 +1000 Message-ID: <20241002055048.556083-23-alistair.francis@wdc.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241002055048.556083-1-alistair.francis@wdc.com> References: <20241002055048.556083-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1727848661545116600 Content-Type: text/plain; charset="utf-8" From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-5-itachis@FreeBSD.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch.h | 27 +++++++++++++++++++++++++++ bsd-user/riscv/target_arch_cpu.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 bsd-user/riscv/target_arch.h create mode 100644 bsd-user/riscv/target_arch_cpu.c diff --git a/bsd-user/riscv/target_arch.h b/bsd-user/riscv/target_arch.h new file mode 100644 index 0000000000..26ce07f343 --- /dev/null +++ b/bsd-user/riscv/target_arch.h @@ -0,0 +1,27 @@ +/* + * RISC-V specific prototypes + * + * Copyright (c) 2019 Mark Corbin + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARCH_H +#define TARGET_ARCH_H + +#include "qemu.h" + +void target_cpu_set_tls(CPURISCVState *env, target_ulong newtls); + +#endif /* TARGET_ARCH_H */ diff --git a/bsd-user/riscv/target_arch_cpu.c b/bsd-user/riscv/target_arch_= cpu.c new file mode 100644 index 0000000000..44e25d2ddf --- /dev/null +++ b/bsd-user/riscv/target_arch_cpu.c @@ -0,0 +1,29 @@ +/* + * RISC-V CPU related code + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ +#include "qemu/osdep.h" + +#include "target_arch.h" + +#define TP_OFFSET 16 + +/* Compare with cpu_set_user_tls() in riscv/riscv/vm_machdep.c */ +void target_cpu_set_tls(CPURISCVState *env, target_ulong newtls) +{ + env->gpr[xTP] =3D newtls + TP_OFFSET; +} --=20 2.46.2