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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20b37e60c76sm78324235ad.269.2024.10.01.22.51.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2024 22:51:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1727848314; x=1728453114; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Yn+cm4ym2epVgTo4WgtcW7AtRv+/gP6vj8Ibil2PIwI=; b=YVV0vNstd/7bTp+N+KXpA96eH+vJ1a5zUbvLrpbVER45ETDRz0Q+vCJDixuEbs9Hvp BQ4XLOJlY3zzBZBhaLBwLxBRceBbQxBgJ+7T6gsh3WN/Gz04msjjXE3qvVjb4NfMV/HG 9P4BptjY+TocmcrDWmY2q+vSxKiPzChdoSbQ+hLP81t3AewCVlC3rP7YVEc3+VHeleVy 5ci4VVyqKEcrsBE8lyx3DH08P3mqQW7275IrTVtbZZ9VMzXxTIpyvgfRt9lry/05gJaW R8wvIWFE9IBoL31LIdj6GNW4hOeYo5ZGQoB2MinbYDBsjDzRUjZUbOz0cDthqyUoYAjM MgPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727848314; x=1728453114; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Yn+cm4ym2epVgTo4WgtcW7AtRv+/gP6vj8Ibil2PIwI=; b=E33nlwystzY7bDRltblgf5t1LwzXVxPqWXKoYfOT5apnzAcL8/lrFGAGWBnA4zTMYL G/trJp3qr0BMXdj6Gv9HO4H04Vs2u46tzML7EUzvpLF/Yu1l5bu1wnB5C+Nn+9AYHZ9A 9TOvo/KzmTyK9jmTs+bQshrAPzMmlxAIXBeLm9jP1azgYjWtvq8hstHyXvKinqS60xa2 iQzQlySLeCKXarEsYfbB+ZbdgkosWxj9yQGpYEGrIgGwGVxy00kwO/SF7Z2LnDCmGcjz 5DAHRADdHyXvILBeRNdY3pngWeQyFkDCL6N0fw2HrSGArkI2CFBO4mWkk+nTrqVTF6/Q Iz7Q== X-Gm-Message-State: AOJu0YzAsojwfAqJ0RvBpmWZqnS5N1oieJgyEV98IPoD7aYBQPu/jNJI wjq/jFUAQM548JCuKMW2I2lfMbWfECQQF7RW0FrvjS7lV1vNG3t2ULb/PxBq X-Google-Smtp-Source: AGHT+IH7wfigb9dL/CNuc0VPZ2FeTJI093f3Wllpl7+RgAVVM0fVVuFjhM0N6Nc6QQhrxlvIM5PiWg== X-Received: by 2002:a17:902:ce8a:b0:20b:61ec:7d3c with SMTP id d9443c01a7336-20bc5a76182mr31263455ad.49.1727848314537; Tue, 01 Oct 2024 22:51:54 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Mark Corbin , Ajeet Singh , Jessica Clarke , Richard Henderson , Alistair Francis Subject: [PULL v3 19/35] bsd-user: Implement RISC-V CPU initialization and main loop Date: Wed, 2 Oct 2024 15:50:32 +1000 Message-ID: <20241002055048.556083-20-alistair.francis@wdc.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241002055048.556083-1-alistair.francis@wdc.com> References: <20241002055048.556083-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=alistair23@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1727848721722116600 Content-Type: text/plain; charset="utf-8" From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-2-itachis@FreeBSD.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_cpu.h | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 bsd-user/riscv/target_arch_cpu.h diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_= cpu.h new file mode 100644 index 0000000000..f8d85e01ad --- /dev/null +++ b/bsd-user/riscv/target_arch_cpu.h @@ -0,0 +1,40 @@ +/* + * RISC-V CPU init and loop + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_CPU_H +#define TARGET_ARCH_CPU_H + +#include "target_arch.h" +#include "signal-common.h" + +#define TARGET_DEFAULT_CPU_MODEL "max" + +static inline void target_cpu_init(CPURISCVState *env, + struct target_pt_regs *regs) +{ + int i; + + for (i =3D 1; i < 32; i++) { + env->gpr[i] =3D regs->regs[i]; + } + + env->pc =3D regs->sepc; +} + +#endif /* TARGET_ARCH_CPU_H */ --=20 2.46.2