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[200.206.229.93]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20b37d63971sm76061295ad.4.2024.10.01.18.03.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2024 18:03:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1727831016; x=1728435816; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N2FlkjWOEsjJoMDEMxy5fL2jBzz/PnyJOUhMSZO37LI=; b=Xi9Ou4s9XhgkkB+TcfKZx77uLDbVLjjO0phxUd0QW/g4lT7ESL2AGCC4/AXQd0thCF EsekRqUBQ/aslvqgaDNQdOob3iyaCVvcOUoXqX6kIJNip4M7AO0O3eBeigtjGyXTgRMQ 5bR/64V7WepdrNCrOf8+m17n4S8QlEQU+N8uHT9NmO9XUx4YgkPx7iAKSD6Iqq2zJgih CHvfHLGVaMUtMpxgECS/sBvhHXrZwKaUlhnh7BmFeWfACWhYf9eXokl6HuGHGXWkal1z Ryy4KUXR6t04GIwLb4qG7Mkqwk13v/vIjsiQDu9laISuflRP0ajwlo5HIoCPlon9RGon SjIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727831016; x=1728435816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N2FlkjWOEsjJoMDEMxy5fL2jBzz/PnyJOUhMSZO37LI=; b=jXVZITH4V/DzX1gWTDBC/Qmzwgsp/cd3OEvde0gF0MFw0UWmuVrypsBw0+tRBIwNvq RHNIzxz70ldGFDbkh5YXsFegKTySt/ezsaUFrdloTQry6tBK+PLUu/Wq4vngbw9tHAXv c86NXIoIyzYIN3YF1Y6I+Gf+/+WF8YjLaIcatx/ddKEW6H6IAGUiwLPXKoajq4K8i1ck Asrnmp5Kq7JQtntKKUsiznNF/1csOiqBKUUQIyZLGh1KKUzVhWOZztsOFUO/I8Ia4Vu4 dUBdFpFiViToT6RNU4mZRjJIl6elrk3LX7OJcdVLaLTHueMAkwk7GTAzsHFIAI/iAX60 yVJQ== X-Gm-Message-State: AOJu0YzKWmRIdrtFIH7wtyFKQVmqjpzCpOhlnJbsxsnPJ7YAClV7qCSX DuvaqzVZCNBDIbYyFvOn+YpOREnzeMFMyM+797LjygtBsm2ueo5rNdwbF+ngaeJDcGl2fGJsz4t u X-Google-Smtp-Source: AGHT+IEfkP3lNvpGk9HH11hmO3khitNzUacDkJASLc8x2JVwss+RLqmr5arMjue8Sk/gbqspofQtNA== X-Received: by 2002:a17:903:234d:b0:20b:7221:ea3d with SMTP id d9443c01a7336-20bc5a41cecmr17832705ad.30.1727831016140; Tue, 01 Oct 2024 18:03:36 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, peter.maydell@linaro.org, Daniel Henrique Barboza , Gerd Hoffmann , Frank Chang Subject: [PATCH v8 04/12] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device Date: Tue, 1 Oct 2024 22:02:59 -0300 Message-ID: <20241002010314.1928515-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002010314.1928515-1-dbarboza@ventanamicro.com> References: <20241002010314.1928515-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1727831078472116600 Content-Type: text/plain; charset="utf-8" The RISC-V IOMMU PCI device we're going to add next is a reference implementation of the riscv-iommu spec [1], which predicts that the IOMMU can be implemented as a PCIe device. However, RISC-V International (RVI), the entity that ratified the riscv-iommu spec, didn't bother assigning a PCI ID for this IOMMU PCIe implementation that the spec predicts. This puts us in an uncommon situation because we want to add the reference IOMMU PCIe implementation but we don't have a PCI ID for it. Given that RVI doesn't provide a PCI ID for it we reached out to Red Hat and Gerd Hoffman, and they were kind enough to give us a PCI ID for the RISC-V IOMMU PCI reference device. Thanks Red Hat and Gerd for this RISC-V IOMMU PCIe device ID. [1] https://github.com/riscv-non-isa/riscv-iommu/releases/tag/v1.0.0 Cc: Gerd Hoffmann Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Reviewed-by: Gerd Hoffmann --- docs/specs/pci-ids.rst | 2 ++ include/hw/pci/pci.h | 1 + 2 files changed, 3 insertions(+) diff --git a/docs/specs/pci-ids.rst b/docs/specs/pci-ids.rst index 328ab31fe8..261b0f359f 100644 --- a/docs/specs/pci-ids.rst +++ b/docs/specs/pci-ids.rst @@ -98,6 +98,8 @@ PCI devices (other than virtio): PCI ACPI ERST device (``-device acpi-erst``) 1b36:0013 PCI UFS device (``-device ufs``) +1b36:0014 + PCI RISC-V IOMMU device =20 All these devices are documented in :doc:`index`. =20 diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index eb26cac810..35d4fe0bbf 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -116,6 +116,7 @@ extern bool pci_available; #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012 #define PCI_DEVICE_ID_REDHAT_UFS 0x0013 +#define PCI_DEVICE_ID_REDHAT_RISCV_IOMMU 0x0014 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 =20 #define FMT_PCIBUS PRIx64 --=20 2.45.2