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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd56e6547sm12243771f8f.58.2024.10.01.09.39.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2024 09:39:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727800785; x=1728405585; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=MyQMYurSoVT4LraZt6ibHbKbByl9wat5HqHvkispgMQ=; b=nijjoxqf3qqrm3VVpeD/cqYn9M9nIY2dXNs5XKCCqVzN0FBA+sx0e7AibRHO6sIw42 5AlzM+uWIfv80Vs8eYeor1QHdodTaQi+rMBvbpcwfVM9SjTD+xS+2uxsITZgzotuKOnK DBnhf7F8K0XxazqUUuctJ/CI6d3k7V5tAIWodWwTNFwnxhn/8mSjAMSCbWwiB7B63U96 RHZ3T6ioKlyvn58Gv/DCapTho1HSDK1gMNmm5bjJkjDfxa6SEw7pYcILQS8oHmyeOloo 6qmUwkArD1q5+e9kPEbBcdxIrw/ZzKbJEorXGUAbpkyUpVP48WpB5/zu8teslNqmAz9H sW1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727800785; x=1728405585; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MyQMYurSoVT4LraZt6ibHbKbByl9wat5HqHvkispgMQ=; b=dtmwC+LmOe+4GStmUbCkDcjtjLKHu99CTewsYeAhPqOg6bX9qtBsRSu2yla23Vyr11 XYpmqw/qcj8Ohs0IQf5fIfRB+/VDbOLnB74/rjdn/3UXywM3HUjIhf/LZdzqGKnwM5Ds Lsi/ATc24kpiIOzfqUIzOLNMoNm7Q5wr0zvu660QOCsOptGJ9aRAGQKbObEYYsPiS2DE XIA/VDyDFinJDIVvir8KEwKZzR+YQPAjBB5Eqd1gWd872aLd1/byV0f3UPfuk0IBokx8 4bMKETVdDQCT3dfngcMS/GXYOiHZAPZt9i+4MOoY8Z2pb8tHEKNkeObtjRsqH3QZgs8Q kgiQ== X-Gm-Message-State: AOJu0YzIv30O8wkC0gKC/73YhnwT1jfSNmW9ZFjgfeDUfKcw/z7gl9An UzJRS2aOd5vLqeojrTbixIzKB7R34DEfzXuR7KnZBs9sBh5se60HAd7LtiiNEfi5Zr9Ltntdf0H v X-Google-Smtp-Source: AGHT+IFfmD0XvzsjqWUpixTLYeNsGuirSdTHgWBAepcmQSpDt9qmBYqUIAKFnv7ueU2R7b2ebXVDgA== X-Received: by 2002:a05:6000:1567:b0:37c:f933:48a9 with SMTP id ffacd0b85a97d-37cfb8b530amr232174f8f.1.1727800785240; Tue, 01 Oct 2024 09:39:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 46/54] hw/timer: Remove omap_gptimer Date: Tue, 1 Oct 2024 17:39:10 +0100 Message-Id: <20241001163918.1275441-47-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001163918.1275441-1-peter.maydell@linaro.org> References: <20241001163918.1275441-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727801261927116600 The omap_gptimer device is only in the OMAP2 SoC, which we are removing. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20240903160751.4100218-45-peter.maydell@linaro.org --- include/hw/arm/omap.h | 8 - hw/timer/omap_gptimer.c | 512 ---------------------------------------- hw/timer/meson.build | 1 - 3 files changed, 521 deletions(-) delete mode 100644 hw/timer/omap_gptimer.c diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 0cbbf2fecb5..cced3d28605 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -676,13 +676,6 @@ struct omap_dma_lcd_channel_s { # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ # define OMAP24XX_DMA_EXT_DMAREQ5 64 =20 -/* omap[123].c */ -/* OMAP2 gp timer */ -struct omap_gp_timer_s; -struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, - qemu_irq irq, omap_clk fclk, omap_clk iclk); -void omap_gp_timer_reset(struct omap_gp_timer_s *s); - /* OMAP2 sysctimer */ struct omap_synctimer_s; struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *t= a, @@ -936,7 +929,6 @@ struct omap_mpu_state_s { /* OMAP2-only peripherals */ struct omap_l4_s *l4; =20 - struct omap_gp_timer_s *gptimer[12]; struct omap_synctimer_s *synctimer; =20 struct omap_mcspi_s *mcspi[2]; diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c deleted file mode 100644 index 34e6af7aff5..00000000000 --- a/hw/timer/omap_gptimer.c +++ /dev/null @@ -1,512 +0,0 @@ -/* - * TI OMAP2 general purpose timers emulation. - * - * Copyright (C) 2007-2008 Nokia Corporation - * Written by Andrzej Zaborowski - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 or - * (at your option) any later version of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, see . - */ - -#include "qemu/osdep.h" -#include "hw/irq.h" -#include "qemu/timer.h" -#include "hw/arm/omap.h" - -/* GP timers */ -struct omap_gp_timer_s { - MemoryRegion iomem; - qemu_irq irq; - qemu_irq wkup; - qemu_irq in; - qemu_irq out; - omap_clk clk; - QEMUTimer *timer; - QEMUTimer *match; - struct omap_target_agent_s *ta; - - int in_val; - int out_val; - int64_t time; - int64_t rate; - int64_t ticks_per_sec; - - int16_t config; - int status; - int it_ena; - int wu_ena; - int enable; - int inout; - int capt2; - int pt; - enum { - gpt_trigger_none, gpt_trigger_overflow, gpt_trigger_both - } trigger; - enum { - gpt_capture_none, gpt_capture_rising, - gpt_capture_falling, gpt_capture_both - } capture; - int scpwm; - int ce; - int pre; - int ptv; - int ar; - int st; - int posted; - uint32_t val; - uint32_t load_val; - uint32_t capture_val[2]; - uint32_t match_val; - int capt_num; - - uint16_t writeh; /* LSB */ - uint16_t readh; /* MSB */ -}; - -#define GPT_TCAR_IT (1 << 2) -#define GPT_OVF_IT (1 << 1) -#define GPT_MAT_IT (1 << 0) - -static inline void omap_gp_timer_intr(struct omap_gp_timer_s *timer, int i= t) -{ - if (timer->it_ena & it) { - if (!timer->status) - qemu_irq_raise(timer->irq); - - timer->status |=3D it; - /* Or are the status bits set even when masked? - * i.e. is masking applied before or after the status register? */ - } - - if (timer->wu_ena & it) - qemu_irq_pulse(timer->wkup); -} - -static inline void omap_gp_timer_out(struct omap_gp_timer_s *timer, int le= vel) -{ - if (!timer->inout && timer->out_val !=3D level) { - timer->out_val =3D level; - qemu_set_irq(timer->out, level); - } -} - -static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer) -{ - uint64_t distance; - - if (timer->st && timer->rate) { - distance =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; - distance =3D muldiv64(distance, timer->rate, timer->ticks_per_sec); - - if (distance >=3D 0xffffffff - timer->val) - return 0xffffffff; - else - return timer->val + distance; - } else - return timer->val; -} - -static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer) -{ - if (timer->st) { - timer->val =3D omap_gp_timer_read(timer); - timer->time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - } -} - -static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer) -{ - int64_t expires, matches; - - if (timer->st && timer->rate) { - expires =3D muldiv64(0x100000000ll - timer->val, - timer->ticks_per_sec, timer->rate); - timer_mod(timer->timer, timer->time + expires); - - if (timer->ce && timer->match_val >=3D timer->val) { - matches =3D muldiv64(timer->ticks_per_sec, - timer->match_val - timer->val, timer->rate); - timer_mod(timer->match, timer->time + matches); - } else - timer_del(timer->match); - } else { - timer_del(timer->timer); - timer_del(timer->match); - omap_gp_timer_out(timer, timer->scpwm); - } -} - -static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer) -{ - if (timer->pt) - /* TODO in overflow-and-match mode if the first event to - * occur is the match, don't toggle. */ - omap_gp_timer_out(timer, !timer->out_val); - else - /* TODO inverted pulse on timer->out_val =3D=3D 1? */ - qemu_irq_pulse(timer->out); -} - -static void omap_gp_timer_tick(void *opaque) -{ - struct omap_gp_timer_s *timer =3D opaque; - - if (!timer->ar) { - timer->st =3D 0; - timer->val =3D 0; - } else { - timer->val =3D timer->load_val; - timer->time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - } - - if (timer->trigger =3D=3D gpt_trigger_overflow || - timer->trigger =3D=3D gpt_trigger_both) - omap_gp_timer_trigger(timer); - - omap_gp_timer_intr(timer, GPT_OVF_IT); - omap_gp_timer_update(timer); -} - -static void omap_gp_timer_match(void *opaque) -{ - struct omap_gp_timer_s *timer =3D opaque; - - if (timer->trigger =3D=3D gpt_trigger_both) - omap_gp_timer_trigger(timer); - - omap_gp_timer_intr(timer, GPT_MAT_IT); -} - -static void omap_gp_timer_input(void *opaque, int line, int on) -{ - struct omap_gp_timer_s *s =3D opaque; - int trigger; - - switch (s->capture) { - default: - case gpt_capture_none: - trigger =3D 0; - break; - case gpt_capture_rising: - trigger =3D !s->in_val && on; - break; - case gpt_capture_falling: - trigger =3D s->in_val && !on; - break; - case gpt_capture_both: - trigger =3D (s->in_val =3D=3D !on); - break; - } - s->in_val =3D on; - - if (s->inout && trigger && s->capt_num < 2) { - s->capture_val[s->capt_num] =3D omap_gp_timer_read(s); - - if (s->capt2 =3D=3D s->capt_num ++) - omap_gp_timer_intr(s, GPT_TCAR_IT); - } -} - -static void omap_gp_timer_clk_update(void *opaque, int line, int on) -{ - struct omap_gp_timer_s *timer =3D opaque; - - omap_gp_timer_sync(timer); - timer->rate =3D on ? omap_clk_getrate(timer->clk) : 0; - omap_gp_timer_update(timer); -} - -static void omap_gp_timer_clk_setup(struct omap_gp_timer_s *timer) -{ - omap_clk_adduser(timer->clk, - qemu_allocate_irq(omap_gp_timer_clk_update, timer, 0)= ); - timer->rate =3D omap_clk_getrate(timer->clk); -} - -void omap_gp_timer_reset(struct omap_gp_timer_s *s) -{ - s->config =3D 0x000; - s->status =3D 0; - s->it_ena =3D 0; - s->wu_ena =3D 0; - s->inout =3D 0; - s->capt2 =3D 0; - s->capt_num =3D 0; - s->pt =3D 0; - s->trigger =3D gpt_trigger_none; - s->capture =3D gpt_capture_none; - s->scpwm =3D 0; - s->ce =3D 0; - s->pre =3D 0; - s->ptv =3D 0; - s->ar =3D 0; - s->st =3D 0; - s->posted =3D 1; - s->val =3D 0x00000000; - s->load_val =3D 0x00000000; - s->capture_val[0] =3D 0x00000000; - s->capture_val[1] =3D 0x00000000; - s->match_val =3D 0x00000000; - omap_gp_timer_update(s); -} - -static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr) -{ - struct omap_gp_timer_s *s =3D opaque; - - switch (addr) { - case 0x00: /* TIDR */ - return 0x21; - - case 0x10: /* TIOCP_CFG */ - return s->config; - - case 0x14: /* TISTAT */ - /* ??? When's this bit reset? */ - return 1; /* RESETDONE */ - - case 0x18: /* TISR */ - return s->status; - - case 0x1c: /* TIER */ - return s->it_ena; - - case 0x20: /* TWER */ - return s->wu_ena; - - case 0x24: /* TCLR */ - return (s->inout << 14) | - (s->capt2 << 13) | - (s->pt << 12) | - (s->trigger << 10) | - (s->capture << 8) | - (s->scpwm << 7) | - (s->ce << 6) | - (s->pre << 5) | - (s->ptv << 2) | - (s->ar << 1) | - (s->st << 0); - - case 0x28: /* TCRR */ - return omap_gp_timer_read(s); - - case 0x2c: /* TLDR */ - return s->load_val; - - case 0x30: /* TTGR */ - return 0xffffffff; - - case 0x34: /* TWPS */ - return 0x00000000; /* No posted writes pending. */ - - case 0x38: /* TMAR */ - return s->match_val; - - case 0x3c: /* TCAR1 */ - return s->capture_val[0]; - - case 0x40: /* TSICR */ - return s->posted << 2; - - case 0x44: /* TCAR2 */ - return s->capture_val[1]; - } - - OMAP_BAD_REG(addr); - return 0; -} - -static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr) -{ - struct omap_gp_timer_s *s =3D opaque; - uint32_t ret; - - if (addr & 2) - return s->readh; - else { - ret =3D omap_gp_timer_readw(opaque, addr); - s->readh =3D ret >> 16; - return ret & 0xffff; - } -} - -static void omap_gp_timer_write(void *opaque, hwaddr addr, uint32_t value) -{ - struct omap_gp_timer_s *s =3D opaque; - - switch (addr) { - case 0x00: /* TIDR */ - case 0x14: /* TISTAT */ - case 0x34: /* TWPS */ - case 0x3c: /* TCAR1 */ - case 0x44: /* TCAR2 */ - OMAP_RO_REG(addr); - break; - - case 0x10: /* TIOCP_CFG */ - s->config =3D value & 0x33d; - if (((value >> 3) & 3) =3D=3D 3) /* IDLEMODE */ - fprintf(stderr, "%s: illegal IDLEMODE value in TIOCP_CFG\n", - __func__); - if (value & 2) /* SOFTRESET */ - omap_gp_timer_reset(s); - break; - - case 0x18: /* TISR */ - if (value & GPT_TCAR_IT) - s->capt_num =3D 0; - if (s->status && !(s->status &=3D ~value)) - qemu_irq_lower(s->irq); - break; - - case 0x1c: /* TIER */ - s->it_ena =3D value & 7; - break; - - case 0x20: /* TWER */ - s->wu_ena =3D value & 7; - break; - - case 0x24: /* TCLR */ - omap_gp_timer_sync(s); - s->inout =3D (value >> 14) & 1; - s->capt2 =3D (value >> 13) & 1; - s->pt =3D (value >> 12) & 1; - s->trigger =3D (value >> 10) & 3; - if (s->capture =3D=3D gpt_capture_none && - ((value >> 8) & 3) !=3D gpt_capture_none) - s->capt_num =3D 0; - s->capture =3D (value >> 8) & 3; - s->scpwm =3D (value >> 7) & 1; - s->ce =3D (value >> 6) & 1; - s->pre =3D (value >> 5) & 1; - s->ptv =3D (value >> 2) & 7; - s->ar =3D (value >> 1) & 1; - s->st =3D (value >> 0) & 1; - if (s->inout && s->trigger !=3D gpt_trigger_none) - fprintf(stderr, "%s: GP timer pin must be an output " - "for this trigger mode\n", __func__); - if (!s->inout && s->capture !=3D gpt_capture_none) - fprintf(stderr, "%s: GP timer pin must be an input " - "for this capture mode\n", __func__); - if (s->trigger =3D=3D gpt_trigger_none) - omap_gp_timer_out(s, s->scpwm); - /* TODO: make sure this doesn't overflow 32-bits */ - s->ticks_per_sec =3D NANOSECONDS_PER_SECOND << (s->pre ? s->ptv + = 1 : 0); - omap_gp_timer_update(s); - break; - - case 0x28: /* TCRR */ - s->time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - s->val =3D value; - omap_gp_timer_update(s); - break; - - case 0x2c: /* TLDR */ - s->load_val =3D value; - break; - - case 0x30: /* TTGR */ - s->time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - s->val =3D s->load_val; - omap_gp_timer_update(s); - break; - - case 0x38: /* TMAR */ - omap_gp_timer_sync(s); - s->match_val =3D value; - omap_gp_timer_update(s); - break; - - case 0x40: /* TSICR */ - s->posted =3D (value >> 2) & 1; - if (value & 2) /* How much exactly are we supposed to reset? */ - omap_gp_timer_reset(s); - break; - - default: - OMAP_BAD_REG(addr); - } -} - -static void omap_gp_timer_writeh(void *opaque, hwaddr addr, uint32_t value) -{ - struct omap_gp_timer_s *s =3D opaque; - - if (addr & 2) - omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh); - else - s->writeh =3D (uint16_t) value; -} - -static uint64_t omap_gp_timer_readfn(void *opaque, hwaddr addr, - unsigned size) -{ - switch (size) { - case 1: - return omap_badwidth_read32(opaque, addr); - case 2: - return omap_gp_timer_readh(opaque, addr); - case 4: - return omap_gp_timer_readw(opaque, addr); - default: - g_assert_not_reached(); - } -} - -static void omap_gp_timer_writefn(void *opaque, hwaddr addr, - uint64_t value, unsigned size) -{ - switch (size) { - case 1: - omap_badwidth_write32(opaque, addr, value); - break; - case 2: - omap_gp_timer_writeh(opaque, addr, value); - break; - case 4: - omap_gp_timer_write(opaque, addr, value); - break; - default: - g_assert_not_reached(); - } -} - -static const MemoryRegionOps omap_gp_timer_ops =3D { - .read =3D omap_gp_timer_readfn, - .write =3D omap_gp_timer_writefn, - .valid.min_access_size =3D 1, - .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, - qemu_irq irq, omap_clk fclk, omap_clk iclk) -{ - struct omap_gp_timer_s *s =3D g_new0(struct omap_gp_timer_s, 1); - - s->ta =3D ta; - s->irq =3D irq; - s->clk =3D fclk; - s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_gp_timer_tick, s); - s->match =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_gp_timer_match, s); - s->in =3D qemu_allocate_irq(omap_gp_timer_input, s, 0); - omap_gp_timer_reset(s); - omap_gp_timer_clk_setup(s); - - memory_region_init_io(&s->iomem, NULL, &omap_gp_timer_ops, s, "omap.gp= timer", - omap_l4_region_size(ta, 0)); - omap_l4_attach(ta, 0, &s->iomem); - - return s; -} diff --git a/hw/timer/meson.build b/hw/timer/meson.build index c1113eb90b1..73cb9541269 100644 --- a/hw/timer/meson.build +++ b/hw/timer/meson.build @@ -21,7 +21,6 @@ system_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mi= ps_gictimer.c')) system_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-timer.c')) system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_timer.c')) system_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_timer.c')) -system_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gptimer.c')) system_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_synctimer.c')) system_ss.add(when: 'CONFIG_PXA2XX_TIMER', if_true: files('pxa2xx_timer.c'= )) system_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_systmr.c')) --=20 2.34.1