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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd56e6547sm12243771f8f.58.2024.10.01.09.39.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2024 09:39:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727800762; x=1728405562; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QS3mui/BYfOr3eX5Vx6VX1RVK+HBTtq1jSdLydD978k=; b=I9o+NyqUkokUJLevNBCNpcafzpD33+zFFLc21uCwaAzRB6Vg8WwBvvUYHLhMefv53b EyhL2TUDBZVpXLwT5KXkAeRsLtEEC9RE42nCMce7lV9epqLpAF9obUPab59eS2syUBAD 0NhFOGlAmDPax1gsGolEyVDbOBGXUVM7IdTjcp4nNaQL8f83e6CW2FdFSFBMVPfPrEnP KIs3qKMUz8FosLovvkV2gGJFnqfVnNw1GhMhz04A9bCKhp75wgECBk2aWvlI7SKrs/po Zq7IevRRnWqolbRDH1CgYKBIb14VE8CRUx9TUYpr/4cm6jVtzUJvdtOtm/D81S3n+0Vg mEKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727800762; x=1728405562; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QS3mui/BYfOr3eX5Vx6VX1RVK+HBTtq1jSdLydD978k=; b=r5fdLkyRwcNC+cWdiK/B02OUexk8Qc2gdwMrzDcBEa2jKt4k9WpSSPeAZ8SPlPfy0t wLugWb+QPGbtfcGAK7uifhXiqr321Y6qiP+IK1Bolj/5Br3AzUiF40qijzcEn6bu1LG9 esmLiYbNYuDndHFPYjqHNsPd8E0zvasi7Wt+Ox79LGkjj0GCxNfyLBSBYqqrvb44oEq+ CP+1RicfEGmxMeLF/QIfiblJDfr6kfHWr6qHFtyWEqwiGq3aY8oy1T7GSE0GG+0bn9bI fW9xBkzb5z7fnEfwkOoE+hd81LKSLlILxF5cZnxIw1NZsfsyfKP7rs/P7xGjO4xeqxnh DJKQ== X-Gm-Message-State: AOJu0YxZcttk5YM4/VouI/e84c4vJsC0huqVD38a+FIt2WIep/LEpIR6 NyGo+RwUIr/sz+khA9gtoMeoHT7iEAJe5oGA+tavSZfLm09TYfWOVgXJq9AIuiMuXDCg9bn9iw6 3 X-Google-Smtp-Source: AGHT+IE1gJN6m51NqlAY8qo4xCz0uETiu5ShqETL4Qk+DkB86yqaooPuO9I5mga2Y0TsyA8t5deobQ== X-Received: by 2002:adf:e711:0:b0:37c:ccbc:6573 with SMTP id ffacd0b85a97d-37cfb8c7618mr120092f8f.18.1727800761497; Tue, 01 Oct 2024 09:39:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/54] m25p80: Add SFDP table for mt35xu01g flash Date: Tue, 1 Oct 2024 17:38:27 +0100 Message-Id: <20241001163918.1275441-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001163918.1275441-1-peter.maydell@linaro.org> References: <20241001163918.1275441-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727801243793116600 Content-Type: text/plain; charset="utf-8" From: Shiva sagar Myana Add the SFDP table for the Micron Xccela mt35xu01g flash. Signed-off-by: Shiva sagar Myana Reviewed-by: Francisco Iglesias Message-id: 20240829120117.616861-1-Shivasagar.Myana@amd.com Signed-off-by: Peter Maydell --- hw/block/m25p80_sfdp.h | 1 + hw/block/m25p80.c | 3 ++- hw/block/m25p80_sfdp.c | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 40 insertions(+), 1 deletion(-) diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h index 1733b569508..89c2d8f72d5 100644 --- a/hw/block/m25p80_sfdp.h +++ b/hw/block/m25p80_sfdp.h @@ -16,6 +16,7 @@ #define M25P80_SFDP_MAX_SIZE (1 << 24) =20 uint8_t m25p80_sfdp_n25q256a(uint32_t addr); +uint8_t m25p80_sfdp_mt35xu01g(uint32_t addr); uint8_t m25p80_sfdp_mt35xu02g(uint32_t addr); =20 uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr); diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 134ee07fbcb..f7123f9e687 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -266,7 +266,8 @@ static const FlashPartInfo known_devices[] =3D { { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) }, { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K= ) }, { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024, - ER_4K | ER_32K, 2) }, + ER_4K | ER_32K, 2), + .sfdp_read =3D m25p80_sfdp_mt35xu01g }, { INFO_STACKED("mt35xu02gbba", 0x2c5b1c, 0x104100, 128 << 10, 2048, ER_4K | ER_32K, 4), .sfdp_read =3D m25p80_sfdp_mt35xu02g }, diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c index 6ee2cfaf119..82d84cc21fe 100644 --- a/hw/block/m25p80_sfdp.c +++ b/hw/block/m25p80_sfdp.c @@ -57,6 +57,43 @@ static const uint8_t sfdp_n25q256a[] =3D { }; define_sfdp_read(n25q256a); =20 +static const uint8_t sfdp_mt35xu01g[] =3D { + 0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff, + 0x00, 0x06, 0x01, 0x10, 0x30, 0x00, 0x00, 0xff, + 0x84, 0x00, 0x01, 0x02, 0x80, 0x00, 0x00, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe5, 0x20, 0x8a, 0xff, 0xff, 0xff, 0xff, 0x3f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xee, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, + 0xff, 0xff, 0x00, 0x00, 0x0c, 0x20, 0x11, 0xd8, + 0x0f, 0x52, 0x00, 0x00, 0x24, 0x5a, 0x99, 0x00, + 0x8b, 0x8e, 0x03, 0xe1, 0xac, 0x01, 0x27, 0x38, + 0x7a, 0x75, 0x7a, 0x75, 0xfb, 0xbd, 0xd5, 0x5c, + 0x00, 0x00, 0x70, 0xff, 0x81, 0xb0, 0x38, 0x36, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x43, 0x0e, 0xff, 0xff, 0x21, 0xdc, 0x5c, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +}; + +define_sfdp_read(mt35xu01g); + static const uint8_t sfdp_mt35xu02g[] =3D { 0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff, 0x00, 0x06, 0x01, 0x10, 0x30, 0x00, 0x00, 0xff, --=20 2.34.1