From nobody Sun Nov 24 04:11:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727801221; cv=none; d=zohomail.com; s=zohoarc; b=G5qch8g6vCEV90hfFCDFFx3iG/5zT5bQxdAB8fCZJNjPBmQAJe79iMLwUySVZFwzDdeP9E2LrqmqOcoZfiSDSzRchzyTSD/1oFdP5crxOaxl4RbrdaQQmKzX/m4lzuXtFBSxrqgpMpfbZdLss3dexGW618I/j0E0HzdZ00BiD2U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727801221; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=gjs5YN8ma0/CyY4dsSuwuOEtEAbDPIv+2IYudABsSBw=; b=h8wLAV95eK/c1D0bKJGcXqlHaBx5REHbvt/VEMWfyp0XHzf/U7kP61gFdtY52ySOePAR1VsnTMl5qMFQNHRbtqt93MvBY4lO7VB/4q3sNFyzNhkRpf1Gi8ECZAKB7L5YbenTF7RpYcjUh4/u/UZLN4TQ0E51ZwiDw4lY1zl0/1A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727801221557874.5428860244202; Tue, 1 Oct 2024 09:47:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svfus-0005sn-82; Tue, 01 Oct 2024 12:40:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svfuW-0005XN-5Y for qemu-devel@nongnu.org; Tue, 01 Oct 2024 12:39:40 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svfuP-00063i-Ok for qemu-devel@nongnu.org; Tue, 01 Oct 2024 12:39:39 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-37cdb6ebc1cso2222408f8f.1 for ; Tue, 01 Oct 2024 09:39:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd56e6547sm12243771f8f.58.2024.10.01.09.39.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2024 09:39:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727800772; x=1728405572; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=gjs5YN8ma0/CyY4dsSuwuOEtEAbDPIv+2IYudABsSBw=; b=vOtrcYN69PQvwqRGDck0LpuatgkYUVhpq7I5xinoWB/fcfkqRLH2Brz6zOrwTZTNid o8nuBfGxneXcC54dOeIXfh/TIuKumkjEV0U14dFahZ4MJ/KWniFM3LcKMNjtuMjLawr1 Wr/MhSuCSKeEKlHygpeP/2TAUn/Bdk9I4DGgSqW0J1DtB2qSyY/+U6RChPtIEpqXlOFe /fq2XgIk8XA59XPTZ6jc/E7yP4IpnFC7apA5KMOzUsNK4lIEPwpGEnv9gBHKaG9iEcfy 01XVvGjNgMiEvdb1JmiEwO1Jzd8Vep6dlnEOQrX75c6e7GpZ5h+8S9Vpp15FwE161WUN JuRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727800772; x=1728405572; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gjs5YN8ma0/CyY4dsSuwuOEtEAbDPIv+2IYudABsSBw=; b=uf1LIZaTdSgxNRww+EkfRkBlxQexjcpoZ82n9BhtAzuJIa5FJlxS7S6xLAySumkL1+ e1/DfZ6F0FANlFZDSDyRuBqIBvpvs+WhIUeFs1SE/8Nqr+6LfoJN66i1Gz3r72t7dRr+ F9wvCc1WfV7kqECVt74QD51YpL2T62oFbt/JOhPuAJdfUhoanPsOGcKcxTunniCJRC17 Gv4EYhHM/f/NbQHxkVEERwVOQyxHSOGCHjPNAyrPI2V2fUgGShyrX6zAJbxC8i5U/LwZ vZZ8cn7LGU+epcVg4/wYLcLU4c+H8jlCnuBQ+If79zhPvkqaZglbxbENmrdhL8/TP+DS GkaA== X-Gm-Message-State: AOJu0YweyHIiFbbPEhn26N06Ic5R1Xq4oO8TdnLFEJ9A2OQQJy4h227D 6u31k8d76wd3w1kJHLzRyhQo0Ga0Kk+INZM9w6TL/tRpvkP8E5MYjoe+5ryNs65evpk5ygYb+6o J X-Google-Smtp-Source: AGHT+IGVp83/dBg7O2ek9U5S5uAxddS5g8NV5jMOWAmI6KXePZ7LarxIAIX6CwNCmg6rXB6uzUn2rg== X-Received: by 2002:adf:eece:0:b0:374:c8d1:70be with SMTP id ffacd0b85a97d-37cfba0a47fmr114672f8f.38.1727800771796; Tue, 01 Oct 2024 09:39:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/54] hw/display: Remove pxa2xx_lcd.c Date: Tue, 1 Oct 2024 17:38:46 +0100 Message-Id: <20241001163918.1275441-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001163918.1275441-1-peter.maydell@linaro.org> References: <20241001163918.1275441-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727801223792116600 Content-Type: text/plain; charset="utf-8" Remove the pxa2xx-specific pxa2xx_lcd device. Signed-off-by: Peter Maydell Message-id: 20240903160751.4100218-19-peter.maydell@linaro.org --- include/hw/arm/pxa.h | 6 - hw/display/pxa2xx_lcd.c | 1451 --------------------------------------- hw/display/meson.build | 1 - 3 files changed, 1458 deletions(-) delete mode 100644 hw/display/pxa2xx_lcd.c diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h index 40f9356b226..ef7976e1821 100644 --- a/include/hw/arm/pxa.h +++ b/include/hw/arm/pxa.h @@ -80,12 +80,6 @@ void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_ir= q handler); DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq); DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq); =20 -/* pxa2xx_lcd.c */ -typedef struct PXA2xxLCDState PXA2xxLCDState; -PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem, - hwaddr base, qemu_irq irq); -void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler); - /* pxa2xx_pcmcia.c */ #define TYPE_PXA2XX_PCMCIA "pxa2xx-pcmcia" OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxPCMCIAState, PXA2XX_PCMCIA) diff --git a/hw/display/pxa2xx_lcd.c b/hw/display/pxa2xx_lcd.c deleted file mode 100644 index a9d0d981a08..00000000000 --- a/hw/display/pxa2xx_lcd.c +++ /dev/null @@ -1,1451 +0,0 @@ -/* - * Intel XScale PXA255/270 LCDC emulation. - * - * Copyright (c) 2006 Openedhand Ltd. - * Written by Andrzej Zaborowski - * - * This code is licensed under the GPLv2. - * - * Contributions after 2012-01-13 are licensed under the terms of the - * GNU GPL, version 2 or (at your option) any later version. - */ - -#include "qemu/osdep.h" -#include "qemu/log.h" -#include "hw/irq.h" -#include "migration/vmstate.h" -#include "ui/console.h" -#include "hw/arm/pxa.h" -#include "ui/pixel_ops.h" -#include "hw/boards.h" -/* FIXME: For graphic_rotate. Should probably be done in common code. */ -#include "sysemu/sysemu.h" -#include "framebuffer.h" - -struct DMAChannel { - uint32_t branch; - uint8_t up; - uint8_t palette[1024]; - uint8_t pbuffer[1024]; - void (*redraw)(PXA2xxLCDState *s, hwaddr addr, - int *miny, int *maxy); - - uint32_t descriptor; - uint32_t source; - uint32_t id; - uint32_t command; -}; - -struct PXA2xxLCDState { - MemoryRegion *sysmem; - MemoryRegion iomem; - MemoryRegionSection fbsection; - qemu_irq irq; - int irqlevel; - - int invalidated; - QemuConsole *con; - int dest_width; - int xres, yres; - int pal_for; - int transp; - enum { - pxa_lcdc_2bpp =3D 1, - pxa_lcdc_4bpp =3D 2, - pxa_lcdc_8bpp =3D 3, - pxa_lcdc_16bpp =3D 4, - pxa_lcdc_18bpp =3D 5, - pxa_lcdc_18pbpp =3D 6, - pxa_lcdc_19bpp =3D 7, - pxa_lcdc_19pbpp =3D 8, - pxa_lcdc_24bpp =3D 9, - pxa_lcdc_25bpp =3D 10, - } bpp; - - uint32_t control[6]; - uint32_t status[2]; - uint32_t ovl1c[2]; - uint32_t ovl2c[2]; - uint32_t ccr; - uint32_t cmdcr; - uint32_t trgbr; - uint32_t tcr; - uint32_t liidr; - uint8_t bscntr; - - struct DMAChannel dma_ch[7]; - - qemu_irq vsync_cb; - int orientation; -}; - -typedef struct QEMU_PACKED { - uint32_t fdaddr; - uint32_t fsaddr; - uint32_t fidr; - uint32_t ldcmd; -} PXAFrameDescriptor; - -#define LCCR0 0x000 /* LCD Controller Control register 0 */ -#define LCCR1 0x004 /* LCD Controller Control register 1 */ -#define LCCR2 0x008 /* LCD Controller Control register 2 */ -#define LCCR3 0x00c /* LCD Controller Control register 3 */ -#define LCCR4 0x010 /* LCD Controller Control register 4 */ -#define LCCR5 0x014 /* LCD Controller Control register 5 */ - -#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */ -#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */ -#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */ -#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */ -#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */ -#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */ -#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */ - -#define LCSR1 0x034 /* LCD Controller Status register 1 */ -#define LCSR0 0x038 /* LCD Controller Status register 0 */ -#define LIIDR 0x03c /* LCD Controller Interrupt ID register */ - -#define TRGBR 0x040 /* TMED RGB Seed register */ -#define TCR 0x044 /* TMED Control register */ - -#define OVL1C1 0x050 /* Overlay 1 Control register 1 */ -#define OVL1C2 0x060 /* Overlay 1 Control register 2 */ -#define OVL2C1 0x070 /* Overlay 2 Control register 1 */ -#define OVL2C2 0x080 /* Overlay 2 Control register 2 */ -#define CCR 0x090 /* Cursor Control register */ - -#define CMDCR 0x100 /* Command Control register */ -#define PRSR 0x104 /* Panel Read Status register */ - -#define PXA_LCDDMA_CHANS 7 -#define DMA_FDADR 0x00 /* Frame Descriptor Address regist= er */ -#define DMA_FSADR 0x04 /* Frame Source Address register */ -#define DMA_FIDR 0x08 /* Frame ID register */ -#define DMA_LDCMD 0x0c /* Command register */ - -/* LCD Buffer Strength Control register */ -#define BSCNTR 0x04000054 - -/* Bitfield masks */ -#define LCCR0_ENB (1 << 0) -#define LCCR0_CMS (1 << 1) -#define LCCR0_SDS (1 << 2) -#define LCCR0_LDM (1 << 3) -#define LCCR0_SOFM0 (1 << 4) -#define LCCR0_IUM (1 << 5) -#define LCCR0_EOFM0 (1 << 6) -#define LCCR0_PAS (1 << 7) -#define LCCR0_DPD (1 << 9) -#define LCCR0_DIS (1 << 10) -#define LCCR0_QDM (1 << 11) -#define LCCR0_PDD (0xff << 12) -#define LCCR0_BSM0 (1 << 20) -#define LCCR0_OUM (1 << 21) -#define LCCR0_LCDT (1 << 22) -#define LCCR0_RDSTM (1 << 23) -#define LCCR0_CMDIM (1 << 24) -#define LCCR0_OUC (1 << 25) -#define LCCR0_LDDALT (1 << 26) -#define LCCR1_PPL(x) ((x) & 0x3ff) -#define LCCR2_LPP(x) ((x) & 0x3ff) -#define LCCR3_API (15 << 16) -#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8)) -#define LCCR3_PDFOR(x) (((x) >> 30) & 3) -#define LCCR4_K1(x) (((x) >> 0) & 7) -#define LCCR4_K2(x) (((x) >> 3) & 7) -#define LCCR4_K3(x) (((x) >> 6) & 7) -#define LCCR4_PALFOR(x) (((x) >> 15) & 3) -#define LCCR5_SOFM(ch) (1 << (ch - 1)) -#define LCCR5_EOFM(ch) (1 << (ch + 7)) -#define LCCR5_BSM(ch) (1 << (ch + 15)) -#define LCCR5_IUM(ch) (1 << (ch + 23)) -#define OVLC1_EN (1 << 31) -#define CCR_CEN (1 << 31) -#define FBR_BRA (1 << 0) -#define FBR_BINT (1 << 1) -#define FBR_SRCADDR (0xfffffff << 4) -#define LCSR0_LDD (1 << 0) -#define LCSR0_SOF0 (1 << 1) -#define LCSR0_BER (1 << 2) -#define LCSR0_ABC (1 << 3) -#define LCSR0_IU0 (1 << 4) -#define LCSR0_IU1 (1 << 5) -#define LCSR0_OU (1 << 6) -#define LCSR0_QD (1 << 7) -#define LCSR0_EOF0 (1 << 8) -#define LCSR0_BS0 (1 << 9) -#define LCSR0_SINT (1 << 10) -#define LCSR0_RDST (1 << 11) -#define LCSR0_CMDINT (1 << 12) -#define LCSR0_BERCH(x) (((x) & 7) << 28) -#define LCSR1_SOF(ch) (1 << (ch - 1)) -#define LCSR1_EOF(ch) (1 << (ch + 7)) -#define LCSR1_BS(ch) (1 << (ch + 15)) -#define LCSR1_IU(ch) (1 << (ch + 23)) -#define LDCMD_LENGTH(x) ((x) & 0x001ffffc) -#define LDCMD_EOFINT (1 << 21) -#define LDCMD_SOFINT (1 << 22) -#define LDCMD_PAL (1 << 26) - -/* Size of a pixel in the QEMU UI output surface, in bytes */ -#define DEST_PIXEL_WIDTH 4 - -/* Line drawing code to handle the various possible guest pixel formats */ - -# define SKIP_PIXEL(to) do { to +=3D deststep; } while (0) -# define COPY_PIXEL(to, from) \ - do { \ - *(uint32_t *) to =3D from; \ - SKIP_PIXEL(to); \ - } while (0) - -#if HOST_BIG_ENDIAN -# define SWAP_WORDS 1 -#endif - -#define FN_2(x) FN(x + 1) FN(x) -#define FN_4(x) FN_2(x + 2) FN_2(x) - -static void pxa2xx_draw_line2(void *opaque, uint8_t *dest, const uint8_t *= src, - int width, int deststep) -{ - uint32_t *palette =3D opaque; - uint32_t data; - while (width > 0) { - data =3D *(uint32_t *) src; -#define FN(x) COPY_PIXEL(dest, palette[(data >> ((x) * 2)) & 3]); -#ifdef SWAP_WORDS - FN_4(12) - FN_4(8) - FN_4(4) - FN_4(0) -#else - FN_4(0) - FN_4(4) - FN_4(8) - FN_4(12) -#endif -#undef FN - width -=3D 16; - src +=3D 4; - } -} - -static void pxa2xx_draw_line4(void *opaque, uint8_t *dest, const uint8_t *= src, - int width, int deststep) -{ - uint32_t *palette =3D opaque; - uint32_t data; - while (width > 0) { - data =3D *(uint32_t *) src; -#define FN(x) COPY_PIXEL(dest, palette[(data >> ((x) * 4)) & 0xf]); -#ifdef SWAP_WORDS - FN_2(6) - FN_2(4) - FN_2(2) - FN_2(0) -#else - FN_2(0) - FN_2(2) - FN_2(4) - FN_2(6) -#endif -#undef FN - width -=3D 8; - src +=3D 4; - } -} - -static void pxa2xx_draw_line8(void *opaque, uint8_t *dest, const uint8_t *= src, - int width, int deststep) -{ - uint32_t *palette =3D opaque; - uint32_t data; - while (width > 0) { - data =3D *(uint32_t *) src; -#define FN(x) COPY_PIXEL(dest, palette[(data >> (x)) & 0xff]); -#ifdef SWAP_WORDS - FN(24) - FN(16) - FN(8) - FN(0) -#else - FN(0) - FN(8) - FN(16) - FN(24) -#endif -#undef FN - width -=3D 4; - src +=3D 4; - } -} - -static void pxa2xx_draw_line16(void *opaque, uint8_t *dest, const uint8_t = *src, - int width, int deststep) -{ - uint32_t data; - unsigned int r, g, b; - while (width > 0) { - data =3D *(uint32_t *) src; -#ifdef SWAP_WORDS - data =3D bswap32(data); -#endif - b =3D (data & 0x1f) << 3; - data >>=3D 5; - g =3D (data & 0x3f) << 2; - data >>=3D 6; - r =3D (data & 0x1f) << 3; - data >>=3D 5; - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - b =3D (data & 0x1f) << 3; - data >>=3D 5; - g =3D (data & 0x3f) << 2; - data >>=3D 6; - r =3D (data & 0x1f) << 3; - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - width -=3D 2; - src +=3D 4; - } -} - -static void pxa2xx_draw_line16t(void *opaque, uint8_t *dest, const uint8_t= *src, - int width, int deststep) -{ - uint32_t data; - unsigned int r, g, b; - while (width > 0) { - data =3D *(uint32_t *) src; -#ifdef SWAP_WORDS - data =3D bswap32(data); -#endif - b =3D (data & 0x1f) << 3; - data >>=3D 5; - g =3D (data & 0x1f) << 3; - data >>=3D 5; - r =3D (data & 0x1f) << 3; - data >>=3D 5; - if (data & 1) { - SKIP_PIXEL(dest); - } else { - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - } - data >>=3D 1; - b =3D (data & 0x1f) << 3; - data >>=3D 5; - g =3D (data & 0x1f) << 3; - data >>=3D 5; - r =3D (data & 0x1f) << 3; - data >>=3D 5; - if (data & 1) { - SKIP_PIXEL(dest); - } else { - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - } - width -=3D 2; - src +=3D 4; - } -} - -static void pxa2xx_draw_line18(void *opaque, uint8_t *dest, const uint8_t = *src, - int width, int deststep) -{ - uint32_t data; - unsigned int r, g, b; - while (width > 0) { - data =3D *(uint32_t *) src; -#ifdef SWAP_WORDS - data =3D bswap32(data); -#endif - b =3D (data & 0x3f) << 2; - data >>=3D 6; - g =3D (data & 0x3f) << 2; - data >>=3D 6; - r =3D (data & 0x3f) << 2; - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - width -=3D 1; - src +=3D 4; - } -} - -/* The wicked packed format */ -static void pxa2xx_draw_line18p(void *opaque, uint8_t *dest, const uint8_t= *src, - int width, int deststep) -{ - uint32_t data[3]; - unsigned int r, g, b; - while (width > 0) { - data[0] =3D *(uint32_t *) src; - src +=3D 4; - data[1] =3D *(uint32_t *) src; - src +=3D 4; - data[2] =3D *(uint32_t *) src; - src +=3D 4; -#ifdef SWAP_WORDS - data[0] =3D bswap32(data[0]); - data[1] =3D bswap32(data[1]); - data[2] =3D bswap32(data[2]); -#endif - b =3D (data[0] & 0x3f) << 2; - data[0] >>=3D 6; - g =3D (data[0] & 0x3f) << 2; - data[0] >>=3D 6; - r =3D (data[0] & 0x3f) << 2; - data[0] >>=3D 12; - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - b =3D (data[0] & 0x3f) << 2; - data[0] >>=3D 6; - g =3D ((data[1] & 0xf) << 4) | (data[0] << 2); - data[1] >>=3D 4; - r =3D (data[1] & 0x3f) << 2; - data[1] >>=3D 12; - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - b =3D (data[1] & 0x3f) << 2; - data[1] >>=3D 6; - g =3D (data[1] & 0x3f) << 2; - data[1] >>=3D 6; - r =3D ((data[2] & 0x3) << 6) | (data[1] << 2); - data[2] >>=3D 8; - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - b =3D (data[2] & 0x3f) << 2; - data[2] >>=3D 6; - g =3D (data[2] & 0x3f) << 2; - data[2] >>=3D 6; - r =3D data[2] << 2; - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - width -=3D 4; - } -} - -static void pxa2xx_draw_line19(void *opaque, uint8_t *dest, const uint8_t = *src, - int width, int deststep) -{ - uint32_t data; - unsigned int r, g, b; - while (width > 0) { - data =3D *(uint32_t *) src; -#ifdef SWAP_WORDS - data =3D bswap32(data); -#endif - b =3D (data & 0x3f) << 2; - data >>=3D 6; - g =3D (data & 0x3f) << 2; - data >>=3D 6; - r =3D (data & 0x3f) << 2; - data >>=3D 6; - if (data & 1) { - SKIP_PIXEL(dest); - } else { - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - } - width -=3D 1; - src +=3D 4; - } -} - -/* The wicked packed format */ -static void pxa2xx_draw_line19p(void *opaque, uint8_t *dest, const uint8_t= *src, - int width, int deststep) -{ - uint32_t data[3]; - unsigned int r, g, b; - while (width > 0) { - data[0] =3D *(uint32_t *) src; - src +=3D 4; - data[1] =3D *(uint32_t *) src; - src +=3D 4; - data[2] =3D *(uint32_t *) src; - src +=3D 4; -# ifdef SWAP_WORDS - data[0] =3D bswap32(data[0]); - data[1] =3D bswap32(data[1]); - data[2] =3D bswap32(data[2]); -# endif - b =3D (data[0] & 0x3f) << 2; - data[0] >>=3D 6; - g =3D (data[0] & 0x3f) << 2; - data[0] >>=3D 6; - r =3D (data[0] & 0x3f) << 2; - data[0] >>=3D 6; - if (data[0] & 1) { - SKIP_PIXEL(dest); - } else { - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - } - data[0] >>=3D 6; - b =3D (data[0] & 0x3f) << 2; - data[0] >>=3D 6; - g =3D ((data[1] & 0xf) << 4) | (data[0] << 2); - data[1] >>=3D 4; - r =3D (data[1] & 0x3f) << 2; - data[1] >>=3D 6; - if (data[1] & 1) { - SKIP_PIXEL(dest); - } else { - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - } - data[1] >>=3D 6; - b =3D (data[1] & 0x3f) << 2; - data[1] >>=3D 6; - g =3D (data[1] & 0x3f) << 2; - data[1] >>=3D 6; - r =3D ((data[2] & 0x3) << 6) | (data[1] << 2); - data[2] >>=3D 2; - if (data[2] & 1) { - SKIP_PIXEL(dest); - } else { - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - } - data[2] >>=3D 6; - b =3D (data[2] & 0x3f) << 2; - data[2] >>=3D 6; - g =3D (data[2] & 0x3f) << 2; - data[2] >>=3D 6; - r =3D data[2] << 2; - data[2] >>=3D 6; - if (data[2] & 1) { - SKIP_PIXEL(dest); - } else { - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - } - width -=3D 4; - } -} - -static void pxa2xx_draw_line24(void *opaque, uint8_t *dest, const uint8_t = *src, - int width, int deststep) -{ - uint32_t data; - unsigned int r, g, b; - while (width > 0) { - data =3D *(uint32_t *) src; -#ifdef SWAP_WORDS - data =3D bswap32(data); -#endif - b =3D data & 0xff; - data >>=3D 8; - g =3D data & 0xff; - data >>=3D 8; - r =3D data & 0xff; - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - width -=3D 1; - src +=3D 4; - } -} - -static void pxa2xx_draw_line24t(void *opaque, uint8_t *dest, const uint8_t= *src, - int width, int deststep) -{ - uint32_t data; - unsigned int r, g, b; - while (width > 0) { - data =3D *(uint32_t *) src; -#ifdef SWAP_WORDS - data =3D bswap32(data); -#endif - b =3D (data & 0x7f) << 1; - data >>=3D 7; - g =3D data & 0xff; - data >>=3D 8; - r =3D data & 0xff; - data >>=3D 8; - if (data & 1) { - SKIP_PIXEL(dest); - } else { - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - } - width -=3D 1; - src +=3D 4; - } -} - -static void pxa2xx_draw_line25(void *opaque, uint8_t *dest, const uint8_t = *src, - int width, int deststep) -{ - uint32_t data; - unsigned int r, g, b; - while (width > 0) { - data =3D *(uint32_t *) src; -#ifdef SWAP_WORDS - data =3D bswap32(data); -#endif - b =3D data & 0xff; - data >>=3D 8; - g =3D data & 0xff; - data >>=3D 8; - r =3D data & 0xff; - data >>=3D 8; - if (data & 1) { - SKIP_PIXEL(dest); - } else { - COPY_PIXEL(dest, rgb_to_pixel32(r, g, b)); - } - width -=3D 1; - src +=3D 4; - } -} - -/* Overlay planes disabled, no transparency */ -static drawfn pxa2xx_draw_fn_32[16] =3D { - [0 ... 0xf] =3D NULL, - [pxa_lcdc_2bpp] =3D pxa2xx_draw_line2, - [pxa_lcdc_4bpp] =3D pxa2xx_draw_line4, - [pxa_lcdc_8bpp] =3D pxa2xx_draw_line8, - [pxa_lcdc_16bpp] =3D pxa2xx_draw_line16, - [pxa_lcdc_18bpp] =3D pxa2xx_draw_line18, - [pxa_lcdc_18pbpp] =3D pxa2xx_draw_line18p, - [pxa_lcdc_24bpp] =3D pxa2xx_draw_line24, -}; - -/* Overlay planes enabled, transparency used */ -static drawfn pxa2xx_draw_fn_32t[16] =3D { - [0 ... 0xf] =3D NULL, - [pxa_lcdc_4bpp] =3D pxa2xx_draw_line4, - [pxa_lcdc_8bpp] =3D pxa2xx_draw_line8, - [pxa_lcdc_16bpp] =3D pxa2xx_draw_line16t, - [pxa_lcdc_19bpp] =3D pxa2xx_draw_line19, - [pxa_lcdc_19pbpp] =3D pxa2xx_draw_line19p, - [pxa_lcdc_24bpp] =3D pxa2xx_draw_line24t, - [pxa_lcdc_25bpp] =3D pxa2xx_draw_line25, -}; - -#undef COPY_PIXEL -#undef SKIP_PIXEL - -#ifdef SWAP_WORDS -# undef SWAP_WORDS -#endif - -/* Route internal interrupt lines to the global IC */ -static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s) -{ - int level =3D 0; - level |=3D (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LD= M); - level |=3D (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SO= FM0); - level |=3D (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IU= M); - level |=3D (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IU= M(1)); - level |=3D (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OU= M); - level |=3D (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QD= M); - level |=3D (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EO= FM0); - level |=3D (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BS= M0); - level |=3D (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RD= STM); - level |=3D (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CM= DIM); - level |=3D (s->status[1] & ~s->control[5]); - - qemu_set_irq(s->irq, !!level); - s->irqlevel =3D level; -} - -/* Set Branch Status interrupt high and poke associated registers */ -static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch) -{ - int unmasked; - if (ch =3D=3D 0) { - s->status[0] |=3D LCSR0_BS0; - unmasked =3D !(s->control[0] & LCCR0_BSM0); - } else { - s->status[1] |=3D LCSR1_BS(ch); - unmasked =3D !(s->control[5] & LCCR5_BSM(ch)); - } - - if (unmasked) { - if (s->irqlevel) - s->status[0] |=3D LCSR0_SINT; - else - s->liidr =3D s->dma_ch[ch].id; - } -} - -/* Set Start Of Frame Status interrupt high and poke associated registers = */ -static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch) -{ - int unmasked; - if (!(s->dma_ch[ch].command & LDCMD_SOFINT)) - return; - - if (ch =3D=3D 0) { - s->status[0] |=3D LCSR0_SOF0; - unmasked =3D !(s->control[0] & LCCR0_SOFM0); - } else { - s->status[1] |=3D LCSR1_SOF(ch); - unmasked =3D !(s->control[5] & LCCR5_SOFM(ch)); - } - - if (unmasked) { - if (s->irqlevel) - s->status[0] |=3D LCSR0_SINT; - else - s->liidr =3D s->dma_ch[ch].id; - } -} - -/* Set End Of Frame Status interrupt high and poke associated registers */ -static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch) -{ - int unmasked; - if (!(s->dma_ch[ch].command & LDCMD_EOFINT)) - return; - - if (ch =3D=3D 0) { - s->status[0] |=3D LCSR0_EOF0; - unmasked =3D !(s->control[0] & LCCR0_EOFM0); - } else { - s->status[1] |=3D LCSR1_EOF(ch); - unmasked =3D !(s->control[5] & LCCR5_EOFM(ch)); - } - - if (unmasked) { - if (s->irqlevel) - s->status[0] |=3D LCSR0_SINT; - else - s->liidr =3D s->dma_ch[ch].id; - } -} - -/* Set Bus Error Status interrupt high and poke associated registers */ -static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch) -{ - s->status[0] |=3D LCSR0_BERCH(ch) | LCSR0_BER; - if (s->irqlevel) - s->status[0] |=3D LCSR0_SINT; - else - s->liidr =3D s->dma_ch[ch].id; -} - -/* Load new Frame Descriptors from DMA */ -static void pxa2xx_descriptor_load(PXA2xxLCDState *s) -{ - PXAFrameDescriptor desc; - hwaddr descptr; - int i; - - for (i =3D 0; i < PXA_LCDDMA_CHANS; i ++) { - s->dma_ch[i].source =3D 0; - - if (!s->dma_ch[i].up) - continue; - - if (s->dma_ch[i].branch & FBR_BRA) { - descptr =3D s->dma_ch[i].branch & FBR_SRCADDR; - if (s->dma_ch[i].branch & FBR_BINT) - pxa2xx_dma_bs_set(s, i); - s->dma_ch[i].branch &=3D ~FBR_BRA; - } else - descptr =3D s->dma_ch[i].descriptor; - - if (!((descptr >=3D PXA2XX_SDRAM_BASE && descptr + - sizeof(desc) <=3D PXA2XX_SDRAM_BASE + current_machine->ra= m_size) || - (descptr >=3D PXA2XX_INTERNAL_BASE && descptr + sizeof(des= c) <=3D - PXA2XX_INTERNAL_BASE + PXA2XX_INTERNAL_SIZE))) { - continue; - } - - cpu_physical_memory_read(descptr, &desc, sizeof(desc)); - s->dma_ch[i].descriptor =3D le32_to_cpu(desc.fdaddr); - s->dma_ch[i].source =3D le32_to_cpu(desc.fsaddr); - s->dma_ch[i].id =3D le32_to_cpu(desc.fidr); - s->dma_ch[i].command =3D le32_to_cpu(desc.ldcmd); - } -} - -static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset, - unsigned size) -{ - PXA2xxLCDState *s =3D (PXA2xxLCDState *) opaque; - int ch; - - switch (offset) { - case LCCR0: - return s->control[0]; - case LCCR1: - return s->control[1]; - case LCCR2: - return s->control[2]; - case LCCR3: - return s->control[3]; - case LCCR4: - return s->control[4]; - case LCCR5: - return s->control[5]; - - case OVL1C1: - return s->ovl1c[0]; - case OVL1C2: - return s->ovl1c[1]; - case OVL2C1: - return s->ovl2c[0]; - case OVL2C2: - return s->ovl2c[1]; - - case CCR: - return s->ccr; - - case CMDCR: - return s->cmdcr; - - case TRGBR: - return s->trgbr; - case TCR: - return s->tcr; - - case 0x200 ... 0x1000: /* DMA per-channel registers */ - ch =3D (offset - 0x200) >> 4; - if (!(ch >=3D 0 && ch < PXA_LCDDMA_CHANS)) - goto fail; - - switch (offset & 0xf) { - case DMA_FDADR: - return s->dma_ch[ch].descriptor; - case DMA_FSADR: - return s->dma_ch[ch].source; - case DMA_FIDR: - return s->dma_ch[ch].id; - case DMA_LDCMD: - return s->dma_ch[ch].command; - default: - goto fail; - } - - case FBR0: - return s->dma_ch[0].branch; - case FBR1: - return s->dma_ch[1].branch; - case FBR2: - return s->dma_ch[2].branch; - case FBR3: - return s->dma_ch[3].branch; - case FBR4: - return s->dma_ch[4].branch; - case FBR5: - return s->dma_ch[5].branch; - case FBR6: - return s->dma_ch[6].branch; - - case BSCNTR: - return s->bscntr; - - case PRSR: - return 0; - - case LCSR0: - return s->status[0]; - case LCSR1: - return s->status[1]; - case LIIDR: - return s->liidr; - - default: - fail: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\= n", - __func__, offset); - } - - return 0; -} - -static void pxa2xx_lcdc_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - PXA2xxLCDState *s =3D (PXA2xxLCDState *) opaque; - int ch; - - switch (offset) { - case LCCR0: - /* ACK Quick Disable done */ - if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB)) - s->status[0] |=3D LCSR0_QD; - - if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT)) { - qemu_log_mask(LOG_UNIMP, - "%s: internal frame buffer unsupported\n", __fun= c__); - } - if ((s->control[3] & LCCR3_API) && - (value & LCCR0_ENB) && !(value & LCCR0_LCDT)) - s->status[0] |=3D LCSR0_ABC; - - s->control[0] =3D value & 0x07ffffff; - pxa2xx_lcdc_int_update(s); - - s->dma_ch[0].up =3D !!(value & LCCR0_ENB); - s->dma_ch[1].up =3D (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS= ); - break; - - case LCCR1: - s->control[1] =3D value; - break; - - case LCCR2: - s->control[2] =3D value; - break; - - case LCCR3: - s->control[3] =3D value & 0xefffffff; - s->bpp =3D LCCR3_BPP(value); - break; - - case LCCR4: - s->control[4] =3D value & 0x83ff81ff; - break; - - case LCCR5: - s->control[5] =3D value & 0x3f3f3f3f; - break; - - case OVL1C1: - if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) { - qemu_log_mask(LOG_UNIMP, "%s: Overlay 1 not supported\n", __fu= nc__); - } - s->ovl1c[0] =3D value & 0x80ffffff; - s->dma_ch[1].up =3D (value & OVLC1_EN) || (s->control[0] & LCCR0_S= DS); - break; - - case OVL1C2: - s->ovl1c[1] =3D value & 0x000fffff; - break; - - case OVL2C1: - if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) { - qemu_log_mask(LOG_UNIMP, "%s: Overlay 2 not supported\n", __fu= nc__); - } - s->ovl2c[0] =3D value & 0x80ffffff; - s->dma_ch[2].up =3D !!(value & OVLC1_EN); - s->dma_ch[3].up =3D !!(value & OVLC1_EN); - s->dma_ch[4].up =3D !!(value & OVLC1_EN); - break; - - case OVL2C2: - s->ovl2c[1] =3D value & 0x007fffff; - break; - - case CCR: - if (!(s->ccr & CCR_CEN) && (value & CCR_CEN)) { - qemu_log_mask(LOG_UNIMP, - "%s: Hardware cursor unimplemented\n", __func__); - } - s->ccr =3D value & 0x81ffffe7; - s->dma_ch[5].up =3D !!(value & CCR_CEN); - break; - - case CMDCR: - s->cmdcr =3D value & 0xff; - break; - - case TRGBR: - s->trgbr =3D value & 0x00ffffff; - break; - - case TCR: - s->tcr =3D value & 0x7fff; - break; - - case 0x200 ... 0x1000: /* DMA per-channel registers */ - ch =3D (offset - 0x200) >> 4; - if (!(ch >=3D 0 && ch < PXA_LCDDMA_CHANS)) - goto fail; - - switch (offset & 0xf) { - case DMA_FDADR: - s->dma_ch[ch].descriptor =3D value & 0xfffffff0; - break; - - default: - goto fail; - } - break; - - case FBR0: - s->dma_ch[0].branch =3D value & 0xfffffff3; - break; - case FBR1: - s->dma_ch[1].branch =3D value & 0xfffffff3; - break; - case FBR2: - s->dma_ch[2].branch =3D value & 0xfffffff3; - break; - case FBR3: - s->dma_ch[3].branch =3D value & 0xfffffff3; - break; - case FBR4: - s->dma_ch[4].branch =3D value & 0xfffffff3; - break; - case FBR5: - s->dma_ch[5].branch =3D value & 0xfffffff3; - break; - case FBR6: - s->dma_ch[6].branch =3D value & 0xfffffff3; - break; - - case BSCNTR: - s->bscntr =3D value & 0xf; - break; - - case PRSR: - break; - - case LCSR0: - s->status[0] &=3D ~(value & 0xfff); - if (value & LCSR0_BER) - s->status[0] &=3D ~LCSR0_BERCH(7); - break; - - case LCSR1: - s->status[1] &=3D ~(value & 0x3e3f3f); - break; - - default: - fail: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\= n", - __func__, offset); - } -} - -static const MemoryRegionOps pxa2xx_lcdc_ops =3D { - .read =3D pxa2xx_lcdc_read, - .write =3D pxa2xx_lcdc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -/* Load new palette for a given DMA channel, convert to internal format */ -static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp) -{ - DisplaySurface *surface =3D qemu_console_surface(s->con); - int i, n, format, r, g, b, alpha; - uint32_t *dest; - uint8_t *src; - s->pal_for =3D LCCR4_PALFOR(s->control[4]); - format =3D s->pal_for; - - switch (bpp) { - case pxa_lcdc_2bpp: - n =3D 4; - break; - case pxa_lcdc_4bpp: - n =3D 16; - break; - case pxa_lcdc_8bpp: - n =3D 256; - break; - default: - return; - } - - src =3D (uint8_t *) s->dma_ch[ch].pbuffer; - dest =3D (uint32_t *) s->dma_ch[ch].palette; - alpha =3D r =3D g =3D b =3D 0; - - for (i =3D 0; i < n; i ++) { - switch (format) { - case 0: /* 16 bpp, no transparency */ - alpha =3D 0; - if (s->control[0] & LCCR0_CMS) { - r =3D g =3D b =3D *(uint16_t *) src & 0xff; - } - else { - r =3D (*(uint16_t *) src & 0xf800) >> 8; - g =3D (*(uint16_t *) src & 0x07e0) >> 3; - b =3D (*(uint16_t *) src & 0x001f) << 3; - } - src +=3D 2; - break; - case 1: /* 16 bpp plus transparency */ - alpha =3D *(uint32_t *) src & (1 << 24); - if (s->control[0] & LCCR0_CMS) - r =3D g =3D b =3D *(uint32_t *) src & 0xff; - else { - r =3D (*(uint32_t *) src & 0xf80000) >> 16; - g =3D (*(uint32_t *) src & 0x00fc00) >> 8; - b =3D (*(uint32_t *) src & 0x0000f8); - } - src +=3D 4; - break; - case 2: /* 18 bpp plus transparency */ - alpha =3D *(uint32_t *) src & (1 << 24); - if (s->control[0] & LCCR0_CMS) - r =3D g =3D b =3D *(uint32_t *) src & 0xff; - else { - r =3D (*(uint32_t *) src & 0xfc0000) >> 16; - g =3D (*(uint32_t *) src & 0x00fc00) >> 8; - b =3D (*(uint32_t *) src & 0x0000fc); - } - src +=3D 4; - break; - case 3: /* 24 bpp plus transparency */ - alpha =3D *(uint32_t *) src & (1 << 24); - if (s->control[0] & LCCR0_CMS) - r =3D g =3D b =3D *(uint32_t *) src & 0xff; - else { - r =3D (*(uint32_t *) src & 0xff0000) >> 16; - g =3D (*(uint32_t *) src & 0x00ff00) >> 8; - b =3D (*(uint32_t *) src & 0x0000ff); - } - src +=3D 4; - break; - } - switch (surface_bits_per_pixel(surface)) { - case 8: - *dest =3D rgb_to_pixel8(r, g, b) | alpha; - break; - case 15: - *dest =3D rgb_to_pixel15(r, g, b) | alpha; - break; - case 16: - *dest =3D rgb_to_pixel16(r, g, b) | alpha; - break; - case 24: - *dest =3D rgb_to_pixel24(r, g, b) | alpha; - break; - case 32: - *dest =3D rgb_to_pixel32(r, g, b) | alpha; - break; - } - dest ++; - } -} - -static inline drawfn pxa2xx_drawfn(PXA2xxLCDState *s) -{ - if (s->transp) { - return pxa2xx_draw_fn_32t[s->bpp]; - } else { - return pxa2xx_draw_fn_32[s->bpp]; - } -} - -static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s, - hwaddr addr, int *miny, int *maxy) -{ - DisplaySurface *surface =3D qemu_console_surface(s->con); - int src_width, dest_width; - drawfn fn =3D pxa2xx_drawfn(s); - if (!fn) - return; - - src_width =3D (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ - if (s->bpp =3D=3D pxa_lcdc_19pbpp || s->bpp =3D=3D pxa_lcdc_18pbpp) - src_width *=3D 3; - else if (s->bpp > pxa_lcdc_16bpp) - src_width *=3D 4; - else if (s->bpp > pxa_lcdc_8bpp) - src_width *=3D 2; - - dest_width =3D s->xres * DEST_PIXEL_WIDTH; - *miny =3D 0; - if (s->invalidated) { - framebuffer_update_memory_section(&s->fbsection, s->sysmem, - addr, s->yres, src_width); - } - framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres, - src_width, dest_width, DEST_PIXEL_WIDTH, - s->invalidated, - fn, s->dma_ch[0].palette, miny, maxy); -} - -static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s, - hwaddr addr, int *miny, int *maxy) -{ - DisplaySurface *surface =3D qemu_console_surface(s->con); - int src_width, dest_width; - drawfn fn =3D pxa2xx_drawfn(s); - if (!fn) - return; - - src_width =3D (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ - if (s->bpp =3D=3D pxa_lcdc_19pbpp || s->bpp =3D=3D pxa_lcdc_18pbpp) - src_width *=3D 3; - else if (s->bpp > pxa_lcdc_16bpp) - src_width *=3D 4; - else if (s->bpp > pxa_lcdc_8bpp) - src_width *=3D 2; - - dest_width =3D s->yres * DEST_PIXEL_WIDTH; - *miny =3D 0; - if (s->invalidated) { - framebuffer_update_memory_section(&s->fbsection, s->sysmem, - addr, s->yres, src_width); - } - framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres, - src_width, DEST_PIXEL_WIDTH, -dest_width, - s->invalidated, - fn, s->dma_ch[0].palette, - miny, maxy); -} - -static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s, - hwaddr addr, int *miny, int *maxy) -{ - DisplaySurface *surface =3D qemu_console_surface(s->con); - int src_width, dest_width; - drawfn fn =3D pxa2xx_drawfn(s); - if (!fn) { - return; - } - - src_width =3D (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ - if (s->bpp =3D=3D pxa_lcdc_19pbpp || s->bpp =3D=3D pxa_lcdc_18pbpp) { - src_width *=3D 3; - } else if (s->bpp > pxa_lcdc_16bpp) { - src_width *=3D 4; - } else if (s->bpp > pxa_lcdc_8bpp) { - src_width *=3D 2; - } - - dest_width =3D s->xres * DEST_PIXEL_WIDTH; - *miny =3D 0; - if (s->invalidated) { - framebuffer_update_memory_section(&s->fbsection, s->sysmem, - addr, s->yres, src_width); - } - framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres, - src_width, -dest_width, -DEST_PIXEL_WIDTH, - s->invalidated, - fn, s->dma_ch[0].palette, miny, maxy); -} - -static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s, - hwaddr addr, int *miny, int *maxy) -{ - DisplaySurface *surface =3D qemu_console_surface(s->con); - int src_width, dest_width; - drawfn fn =3D pxa2xx_drawfn(s); - if (!fn) { - return; - } - - src_width =3D (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ - if (s->bpp =3D=3D pxa_lcdc_19pbpp || s->bpp =3D=3D pxa_lcdc_18pbpp) { - src_width *=3D 3; - } else if (s->bpp > pxa_lcdc_16bpp) { - src_width *=3D 4; - } else if (s->bpp > pxa_lcdc_8bpp) { - src_width *=3D 2; - } - - dest_width =3D s->yres * DEST_PIXEL_WIDTH; - *miny =3D 0; - if (s->invalidated) { - framebuffer_update_memory_section(&s->fbsection, s->sysmem, - addr, s->yres, src_width); - } - framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres, - src_width, -DEST_PIXEL_WIDTH, dest_width, - s->invalidated, - fn, s->dma_ch[0].palette, - miny, maxy); -} - -static void pxa2xx_lcdc_resize(PXA2xxLCDState *s) -{ - int width, height; - if (!(s->control[0] & LCCR0_ENB)) - return; - - width =3D LCCR1_PPL(s->control[1]) + 1; - height =3D LCCR2_LPP(s->control[2]) + 1; - - if (width !=3D s->xres || height !=3D s->yres) { - if (s->orientation =3D=3D 90 || s->orientation =3D=3D 270) { - qemu_console_resize(s->con, height, width); - } else { - qemu_console_resize(s->con, width, height); - } - s->invalidated =3D 1; - s->xres =3D width; - s->yres =3D height; - } -} - -static void pxa2xx_update_display(void *opaque) -{ - PXA2xxLCDState *s =3D (PXA2xxLCDState *) opaque; - hwaddr fbptr; - int miny, maxy; - int ch; - if (!(s->control[0] & LCCR0_ENB)) - return; - - pxa2xx_descriptor_load(s); - - pxa2xx_lcdc_resize(s); - miny =3D s->yres; - maxy =3D 0; - s->transp =3D s->dma_ch[2].up || s->dma_ch[3].up; - /* Note: With overlay planes the order depends on LCCR0 bit 25. */ - for (ch =3D 0; ch < PXA_LCDDMA_CHANS; ch ++) - if (s->dma_ch[ch].up) { - if (!s->dma_ch[ch].source) { - pxa2xx_dma_ber_set(s, ch); - continue; - } - fbptr =3D s->dma_ch[ch].source; - if (!((fbptr >=3D PXA2XX_SDRAM_BASE && - fbptr <=3D PXA2XX_SDRAM_BASE + current_machine->ram_s= ize) || - (fbptr >=3D PXA2XX_INTERNAL_BASE && - fbptr <=3D PXA2XX_INTERNAL_BASE + PXA2XX_INTERNAL_SIZ= E))) { - pxa2xx_dma_ber_set(s, ch); - continue; - } - - if (s->dma_ch[ch].command & LDCMD_PAL) { - cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer, - MAX(LDCMD_LENGTH(s->dma_ch[ch].command), - sizeof(s->dma_ch[ch].pbuffer))); - pxa2xx_palette_parse(s, ch, s->bpp); - } else { - /* Do we need to reparse palette */ - if (LCCR4_PALFOR(s->control[4]) !=3D s->pal_for) - pxa2xx_palette_parse(s, ch, s->bpp); - - /* ACK frame start */ - pxa2xx_dma_sof_set(s, ch); - - s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy); - s->invalidated =3D 0; - - /* ACK frame completed */ - pxa2xx_dma_eof_set(s, ch); - } - } - - if (s->control[0] & LCCR0_DIS) { - /* ACK last frame completed */ - s->control[0] &=3D ~LCCR0_ENB; - s->status[0] |=3D LCSR0_LDD; - } - - if (miny >=3D 0) { - switch (s->orientation) { - case 0: - dpy_gfx_update(s->con, 0, miny, s->xres, maxy - miny + 1); - break; - case 90: - dpy_gfx_update(s->con, miny, 0, maxy - miny + 1, s->xres); - break; - case 180: - maxy =3D s->yres - maxy - 1; - miny =3D s->yres - miny - 1; - dpy_gfx_update(s->con, 0, maxy, s->xres, miny - maxy + 1); - break; - case 270: - maxy =3D s->yres - maxy - 1; - miny =3D s->yres - miny - 1; - dpy_gfx_update(s->con, maxy, 0, miny - maxy + 1, s->xres); - break; - } - } - pxa2xx_lcdc_int_update(s); - - qemu_irq_raise(s->vsync_cb); -} - -static void pxa2xx_invalidate_display(void *opaque) -{ - PXA2xxLCDState *s =3D (PXA2xxLCDState *) opaque; - s->invalidated =3D 1; -} - -static void pxa2xx_lcdc_orientation(void *opaque, int angle) -{ - PXA2xxLCDState *s =3D (PXA2xxLCDState *) opaque; - - switch (angle) { - case 0: - s->dma_ch[0].redraw =3D pxa2xx_lcdc_dma0_redraw_rot0; - break; - case 90: - s->dma_ch[0].redraw =3D pxa2xx_lcdc_dma0_redraw_rot90; - break; - case 180: - s->dma_ch[0].redraw =3D pxa2xx_lcdc_dma0_redraw_rot180; - break; - case 270: - s->dma_ch[0].redraw =3D pxa2xx_lcdc_dma0_redraw_rot270; - break; - } - - s->orientation =3D angle; - s->xres =3D s->yres =3D -1; - pxa2xx_lcdc_resize(s); -} - -static const VMStateDescription vmstate_dma_channel =3D { - .name =3D "dma_channel", - .version_id =3D 0, - .minimum_version_id =3D 0, - .fields =3D (const VMStateField[]) { - VMSTATE_UINT32(branch, struct DMAChannel), - VMSTATE_UINT8(up, struct DMAChannel), - VMSTATE_BUFFER(pbuffer, struct DMAChannel), - VMSTATE_UINT32(descriptor, struct DMAChannel), - VMSTATE_UINT32(source, struct DMAChannel), - VMSTATE_UINT32(id, struct DMAChannel), - VMSTATE_UINT32(command, struct DMAChannel), - VMSTATE_END_OF_LIST() - } -}; - -static int pxa2xx_lcdc_post_load(void *opaque, int version_id) -{ - PXA2xxLCDState *s =3D opaque; - - s->bpp =3D LCCR3_BPP(s->control[3]); - s->xres =3D s->yres =3D s->pal_for =3D -1; - - return 0; -} - -static const VMStateDescription vmstate_pxa2xx_lcdc =3D { - .name =3D "pxa2xx_lcdc", - .version_id =3D 0, - .minimum_version_id =3D 0, - .post_load =3D pxa2xx_lcdc_post_load, - .fields =3D (const VMStateField[]) { - VMSTATE_INT32(irqlevel, PXA2xxLCDState), - VMSTATE_INT32(transp, PXA2xxLCDState), - VMSTATE_UINT32_ARRAY(control, PXA2xxLCDState, 6), - VMSTATE_UINT32_ARRAY(status, PXA2xxLCDState, 2), - VMSTATE_UINT32_ARRAY(ovl1c, PXA2xxLCDState, 2), - VMSTATE_UINT32_ARRAY(ovl2c, PXA2xxLCDState, 2), - VMSTATE_UINT32(ccr, PXA2xxLCDState), - VMSTATE_UINT32(cmdcr, PXA2xxLCDState), - VMSTATE_UINT32(trgbr, PXA2xxLCDState), - VMSTATE_UINT32(tcr, PXA2xxLCDState), - VMSTATE_UINT32(liidr, PXA2xxLCDState), - VMSTATE_UINT8(bscntr, PXA2xxLCDState), - VMSTATE_STRUCT_ARRAY(dma_ch, PXA2xxLCDState, 7, 0, - vmstate_dma_channel, struct DMAChannel), - VMSTATE_END_OF_LIST() - } -}; - -static const GraphicHwOps pxa2xx_ops =3D { - .invalidate =3D pxa2xx_invalidate_display, - .gfx_update =3D pxa2xx_update_display, -}; - -PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem, - hwaddr base, qemu_irq irq) -{ - PXA2xxLCDState *s; - - s =3D g_new0(PXA2xxLCDState, 1); - s->invalidated =3D 1; - s->irq =3D irq; - s->sysmem =3D sysmem; - - pxa2xx_lcdc_orientation(s, graphic_rotate); - - memory_region_init_io(&s->iomem, NULL, &pxa2xx_lcdc_ops, s, - "pxa2xx-lcd-controller", 0x00100000); - memory_region_add_subregion(sysmem, base, &s->iomem); - - s->con =3D graphic_console_init(NULL, 0, &pxa2xx_ops, s); - - vmstate_register(NULL, 0, &vmstate_pxa2xx_lcdc, s); - - return s; -} - -void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler) -{ - s->vsync_cb =3D handler; -} diff --git a/hw/display/meson.build b/hw/display/meson.build index dabc0d1da6b..1f965a1be84 100644 --- a/hw/display/meson.build +++ b/hw/display/meson.build @@ -27,7 +27,6 @@ system_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exy= nos4210_fimd.c')) system_ss.add(when: 'CONFIG_FRAMEBUFFER', if_true: files('framebuffer.c')) =20 system_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dss.c')) -system_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_lcd.c')) system_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_fb.c')) system_ss.add(when: 'CONFIG_SM501', if_true: files('sm501.c')) system_ss.add(when: 'CONFIG_TCX', if_true: files('tcx.c')) --=20 2.34.1