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[92.88.170.46]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c299ac60sm596492866b.221.2024.09.30.15.12.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 15:12:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727734345; x=1728339145; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=grjpT5kTsMGjq3j1/lhkj4QBsxYe83DKBpMh5569Dgk=; b=oSF4xcxeKpE9rOxFKXgwYX/rgsKqXmEebX3rX+TPysuaXUbwll4HfpAr9tDt8ugRZ1 QbLlLPuC5APuBkiiEpF71ap/Ry8PeWohncBn0Dw4FekV78+YuDOwkMfyz9fotNg1RGb7 Av2+7KEB9zVA+M/TWs+JLLhQ27RGKjjUxRnem1Bwmqy7oc4vuHoeluQHBXQTLgbcWtP/ yMtfv8an3VCF5hAHWco6y3J2bdXCSsv68umCbCp9+1M0OwrknQxkyMZfsSQbQt49iZmd PBTP8BoXKiojN3ghkZzU1eyfeX2XoXuyVWEkAtaXA3gwt5uNYUlGqSnGh7vpJfgeWNWT 0Z6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727734345; x=1728339145; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=grjpT5kTsMGjq3j1/lhkj4QBsxYe83DKBpMh5569Dgk=; b=OKi7Zl/qH9HKov04XGwsy6ohN+34NO/+Bu1YrrHDPcuZjyHzC3UocdSBh8O6HbjeT+ gkltoAiXeuf69ekI0N91TjeICiX4QQ2I8KifVwhXWfucUT+9rvZlw5o7ioDaUVLbhjWD povbnMxt0nGuH69tdmFln32o1kiPyTvjhfx3mSkC1UTBEI8lZVLwPpcNDzBwwkliXQ1x K8hAqtD2cOpgvlfvmxEMxxnoDS841wbgr8J74YJtYfMBh+dhDp4doD8XfFfWo7SaZ99n muTuv5FgYBR2EXiAkDuO8WV+ntDRi5SNxykFvcIUStwxxz0xAr7t0pacj6/wHJMmLimn vZXQ== X-Gm-Message-State: AOJu0YzYAcvJACtVIf3nvTUxS7lPfJbu8ra8Jgp+oLKaKw4DosfDogbG MJjtX7WYgd3hTlZG2o4HGGSLls1qVPcKYNj1qdl9JuJ2mvkLK+jaBlkxxNFutwT3lkf6TLNyi1L DnIE= X-Google-Smtp-Source: AGHT+IEPcXLt1smhJ29KzmCwdkPXbe7bSABmFoFrN9SDqqX5WbSIEsUbxQdEZD9tZa3e3hF5oGDGhA== X-Received: by 2002:a17:907:928b:b0:a89:f5f6:395 with SMTP id a640c23a62f3a-a93c48f0902mr1722277466b.1.1727734344660; Mon, 30 Sep 2024 15:12:24 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Peter Maydell , Thomas Huth , Hao Wu , Laurent Vivier , Joel Stanley , qemu-arm@nongnu.org, Andrew Jeffery , Steven Lee , Tyrone Ting , "Edgar E. Iglesias" , Igor Mitsyanko , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Jamin Lin , Troy Lee , Anton Johansson Subject: [PATCH 2/3] hw/arm: Have arm_write_bootloader() take a ARMCPU argument Date: Tue, 1 Oct 2024 00:12:03 +0200 Message-ID: <20240930221205.59101-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930221205.59101-1-philmd@linaro.org> References: <20240930221205.59101-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727734407445116600 The next commit will replace tswap32() calls by stl_endian_p() ones in bootloader.c. In order to do that, we'll need to know the vCPU endianness. This information is retrievable with arm_cpu_code_is_big_endian(), but we need to access CPUARMState. As a first step, pass ARMCPU as argument to arm_write_bootloader() so it'll be able to access cpu->env. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/boot.h | 9 ++++++--- hw/arm/aspeed.c | 3 +-- hw/arm/boot.c | 9 +++++---- hw/arm/raspi.c | 4 ++-- 4 files changed, 14 insertions(+), 11 deletions(-) diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h index 80c492d742..3d1226ab00 100644 --- a/include/hw/arm/boot.h +++ b/include/hw/arm/boot.h @@ -206,13 +206,15 @@ typedef struct ARMInsnFixup { /** * arm_write_bootloader - write a bootloader to guest memory * @name: name of the bootloader blob - * @as: AddressSpace to write the bootloader + * @cpu: handle to the first CPU object + * @info: handle to the boot info struct * @addr: guest address to write it * @insns: the blob to be loaded * @fixupcontext: context to be used for any fixups in @insns * * Write a bootloader to guest memory at address @addr in the address - * space @as. @name is the name to use for the resulting ROM blob, so + * space returned by @arm_boot_address_space(). + * @name is the name to use for the resulting ROM blob, so * it should be unique in the system and reasonably identifiable for debug= ging. * * @insns must be an array of ARMInsnFixup structs, each of which has @@ -228,7 +230,8 @@ typedef struct ARMInsnFixup { * the entries that @insns refers to. */ void arm_write_bootloader(const char *name, - AddressSpace *as, hwaddr addr, + ARMCPU *cpu, const struct arm_boot_info *info, + hwaddr addr, const ARMInsnFixup *insns, const uint32_t *fixupcontext); =20 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index cf0c6c580b..cf5fb92238 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -217,7 +217,6 @@ struct AspeedMachineState { static void aspeed_write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) { - AddressSpace *as =3D arm_boot_address_space(cpu, info); static const ARMInsnFixup poll_mailbox_ready[] =3D { /* * r2 =3D per-cpu go sign value @@ -244,7 +243,7 @@ static void aspeed_write_smpboot(ARMCPU *cpu, }; static const uint32_t fixupcontext[FIXUP_MAX] =3D { 0 }; =20 - arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, + arm_write_bootloader("aspeed.smpboot", cpu, info, info->smp_loader_sta= rt, poll_mailbox_ready, fixupcontext); } =20 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 5301d8d318..6efd21f9c2 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -131,10 +131,12 @@ static const ARMInsnFixup smpboot[] =3D { }; =20 void arm_write_bootloader(const char *name, - AddressSpace *as, hwaddr addr, + ARMCPU *cpu, const struct arm_boot_info *info, + hwaddr addr, const ARMInsnFixup *insns, const uint32_t *fixupcontext) { + AddressSpace *as =3D arm_boot_address_space(cpu, info); /* Fix up the specified bootloader fragment and write it into * guest memory using rom_add_blob_fixed(). fixupcontext is * an array giving the values to write in for the fixup types @@ -185,7 +187,6 @@ static void default_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) { uint32_t fixupcontext[FIXUP_MAX]; - AddressSpace *as =3D arm_boot_address_space(cpu, info); =20 fixupcontext[FIXUP_GIC_CPU_IF] =3D info->gic_cpu_if_addr; fixupcontext[FIXUP_BOOTREG] =3D info->smp_bootreg_addr; @@ -195,7 +196,7 @@ static void default_write_secondary(ARMCPU *cpu, fixupcontext[FIXUP_DSB] =3D CP15_DSB_INSN; } =20 - arm_write_bootloader("smpboot", as, info->smp_loader_start, + arm_write_bootloader("smpboot", cpu, info, info->smp_loader_start, smpboot, fixupcontext); } =20 @@ -1128,7 +1129,7 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, fixupcontext[FIXUP_ENTRYPOINT_LO] =3D entry; fixupcontext[FIXUP_ENTRYPOINT_HI] =3D entry >> 32; =20 - arm_write_bootloader("bootloader", as, info->loader_start, + arm_write_bootloader("bootloader", cpu, info, info->loader_start, primary_loader, fixupcontext); =20 if (info->write_board_setup) { diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index a7a662f40d..84fffe2a02 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -137,7 +137,7 @@ static void write_smpboot(ARMCPU *cpu, const struct arm= _boot_info *info) QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) !=3D 0 || (BOARDSETUP_ADDR >> 4) >=3D 0x100); =20 - arm_write_bootloader("raspi_smpboot", arm_boot_address_space(cpu, info= ), + arm_write_bootloader("raspi_smpboot", cpu, info, info->smp_loader_start, smpboot, fixupcontext); } =20 @@ -172,7 +172,7 @@ static void write_smpboot64(ARMCPU *cpu, const struct a= rm_boot_info *info) 0, 0, 0, 0 }; =20 - arm_write_bootloader("raspi_smpboot", as, info->smp_loader_start, + arm_write_bootloader("raspi_smpboot", cpu, info, info->smp_loader_star= t, smpboot, fixupcontext); rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintable= s), SPINTABLE_ADDR, as); --=20 2.45.2