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a="26721854" X-IronPort-AV: E=Sophos;i="6.11,165,1725346800"; d="scan'208";a="26721854" X-CSE-ConnectionGUID: lfJb0AUvSuWKT8qGunn6mA== X-CSE-MsgGUID: 65058/OASRqQMrCtWhMVuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,165,1725346800"; d="scan'208";a="77749872" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v4 13/17] intel_iommu: piotlb invalidation should notify unmap Date: Mon, 30 Sep 2024 17:26:27 +0800 Message-Id: <20240930092631.2997543-14-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240930092631.2997543-1-zhenzhong.duan@intel.com> References: <20240930092631.2997543-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.095, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1727688740363116600 This is used by some emulated devices which caches address translation result. When piotlb invalidation issued in guest, those caches should be refreshed. For device that does not implement ATS capability or disable it but still caches the translation result, it is better to implement ATS cap or enable it if there is need to cache the translation result. Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan Reviewed-by: Cl=C3=A9ment Mathieu--Drif Acked-by: Jason Wang --- hw/i386/intel_iommu.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 5ea59167b3..91d7b1abfa 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2908,7 +2908,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, continue; } =20 - if (!s->scalable_modern) { + if (!s->scalable_modern || !vtd_as_has_map_notifier(vtd_as)) { vtd_address_space_sync(vtd_as); } } @@ -2920,6 +2920,9 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUStat= e *s, uint16_t domain_id, bool ih) { VTDIOTLBPageInvInfo info; + VTDAddressSpace *vtd_as; + VTDContextEntry ce; + hwaddr size =3D (1 << am) * VTD_PAGE_SIZE; =20 info.domain_id =3D domain_id; info.pasid =3D pasid; @@ -2930,6 +2933,36 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUSta= te *s, uint16_t domain_id, g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page_piotlb, &info); vtd_iommu_unlock(s); + + QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { + if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), + vtd_as->devfn, &ce) && + domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pasid)) { + uint32_t rid2pasid =3D VTD_CE_GET_RID2PASID(&ce); + IOMMUTLBEvent event; + + if ((vtd_as->pasid !=3D PCI_NO_PASID || pasid !=3D rid2pasid) = && + vtd_as->pasid !=3D pasid) { + continue; + } + + /* + * Page-Selective-within-PASID PASID-based-IOTLB Invalidation + * does not flush stage-2 entries. See spec section 6.5.2.4 + */ + if (!s->scalable_modern) { + continue; + } + + event.type =3D IOMMU_NOTIFIER_UNMAP; + event.entry.target_as =3D &address_space_memory; + event.entry.iova =3D addr; + event.entry.perm =3D IOMMU_NONE; + event.entry.addr_mask =3D size - 1; + event.entry.translated_addr =3D 0; + memory_region_notify_iommu(&vtd_as->iommu, 0, event); + } + } } =20 static bool vtd_process_piotlb_desc(IntelIOMMUState *s, --=20 2.34.1