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[88.28.18.183]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e96a362bcsm144722025e9.36.2024.09.30.02.12.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 02:12:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727687525; x=1728292325; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yZ3s4BKBUIpf605yoFIcvuj2HOu5NdByFuIUuDf7Wlk=; b=kbNjyS7Art1bzFQ8q78iPqr0pPFkUBNtsOocIeDfsZhl7jRVgwfvTIHhHOJOEmH+Rk ilMrRyuN7oKVzRNapoi0iqsTGt99OpRfnJyc0UEVDHihuUvZx6v/h5LSbCKdiqnc6YaJ lPQ3dHn/i3utVcdGmKOBBYLoFiHS0SyZb2tvsshcyk3jDa+zhwslZGhx4QsBOOmsijYM 8O1G75zjHGGPA8a0l/0Fe+0KHz0lx9zFK0OzJ83//PF27J/a8rP75KManXJaKDgitF2C hv/oOQyZemE/oWIXxBoZyq/7ad+PWsG4I10ZXIrx1qaeDprend74sR30vQxLdbgOiD66 mz4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727687525; x=1728292325; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yZ3s4BKBUIpf605yoFIcvuj2HOu5NdByFuIUuDf7Wlk=; b=Q6UxFvAmgx4T3tYqZsl/Gks4ua/RyqmYOPDu+3Ieskdidu8bXpUAGyPYTP9VS/3ORb aWcOi9KciFmcKk4YCozqcua/hkplyk2/PvFMUl3dEId2nepPa6v/m4VgsNLc7epJKtvF PmmQ6K0LgI16rz+ZnxqCZoBgRcagl3xZUDcJVtq5nbYNDBQnbmUzN7HnDRgubYkiuq6Z t+pV2XmovRXnWoa0SWofmSwSnU6hziy+ZRqZ9NFfK8jtyEHrNBiQBITh9qITOu9ZUP7K Nnt4h7uDTpw+y9gP2wQTPHDpBfUUc3bT+QeGODk0xVu+oqgy83rog63xPRrleEn2W16G 9g1A== X-Gm-Message-State: AOJu0Yyf2WApoiH4qDUvu3ByTIVY+BYLZjpDNU/ghtnt+D9emkAM/FvD Kooqac3ycet/V0Ycp4XuVth7ZRx/o6f5QPGT6egPIkaR7KXSOy4XdqgzBs2HrAwjtYJKpr/Tz9n e X-Google-Smtp-Source: AGHT+IESSYBEffHZ9mn3SZL6r9LRgoZ2v0CCuUL5iPDughSA3ypcTq5hwUBQVEPDZiam+pOV48FEXA== X-Received: by 2002:a05:600c:1ca2:b0:428:f0c2:ef4a with SMTP id 5b1f17b1804b1-42f58433166mr75603565e9.13.1727687525081; Mon, 30 Sep 2024 02:12:05 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson Subject: [PATCH 08/12] target/mips: Expose MIPSCPU::is_big_endian property Date: Mon, 30 Sep 2024 11:10:57 +0200 Message-ID: <20240930091101.40591-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930091101.40591-1-philmd@linaro.org> References: <20240930091101.40591-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727687602892116600 Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.h | 3 +++ target/mips/cpu.c | 9 ++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3e906a175a..070e11fe0d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1209,6 +1209,9 @@ struct ArchCPU { =20 Clock *clock; Clock *count_div; /* Divider for CP0_Count clock */ + + /* Properties */ + bool is_big_endian; }; =20 /** diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 89655b1900..982f5bb4e2 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -200,7 +200,8 @@ static void mips_cpu_reset_hold(Object *obj, ResetType = type) =20 /* Reset registers to their default values */ env->CP0_PRid =3D env->cpu_model->CP0_PRid; - env->CP0_Config0 =3D env->cpu_model->CP0_Config0; + env->CP0_Config0 =3D deposit32(env->cpu_model->CP0_Config0, + CP0C0_BE, 1, cpu->is_big_endian); #if TARGET_BIG_ENDIAN env->CP0_Config0 |=3D (1 << CP0C0_BE); #endif @@ -541,6 +542,11 @@ static const struct SysemuCPUOps mips_sysemu_ops =3D { }; #endif =20 +static Property mips_cpu_properties[] =3D { + DEFINE_PROP_BOOL("big-endian", MIPSCPU, is_big_endian, TARGET_BIG_ENDI= AN), + DEFINE_PROP_END_OF_LIST(), +}; + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" /* @@ -571,6 +577,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) DeviceClass *dc =3D DEVICE_CLASS(c); ResettableClass *rc =3D RESETTABLE_CLASS(c); =20 + device_class_set_props(dc, mips_cpu_properties); device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL, --=20 2.45.2