From nobody Sat Dec 21 15:47:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727687508; cv=none; d=zohomail.com; s=zohoarc; b=Em9cM+naPBpyshxVz96IAwbexrqTqQSRFku+uovAbB1gWmSsjhTb5ULicnAM3KgPpIzmIkhQHHcgK1DLW4vmlVIsbC6zQHWxjItKiM7rBbjEOzDOLdcN65qpL/yHywTL6IoOfQT8xMyPwFeADIKsnLaAWD0/XF/qVKLCIapmgh0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727687508; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CFaQW0OfcXDNSv5OAJ0dPlLZ03IofsgYwsxu/4pf3Z8=; b=Dhhdv0KP3RAqcEKuR7zlSvQIgf3MbFMm0btdOmqwEyjpDbKSXuRVH7TwqAqdYz2PlXRhGhy9QRhEc78/ZAJxAnLpfe4w6BjyCs3K8pNri2+MlYpmiuRM7SCqQ5nDdys+WpknZ/+ls9mjtZb+2AiP9MH9lzSIwiTHqQov8GD6mLg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727687508394442.37784462235345; Mon, 30 Sep 2024 02:11:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svCR5-0007SQ-Nv; Mon, 30 Sep 2024 05:11:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svCR2-0007IF-MJ for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:11:16 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svCR0-0004U3-WA for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:11:16 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-42cb8dac900so39516685e9.3 for ; Mon, 30 Sep 2024 02:11:14 -0700 (PDT) Received: from localhost.localdomain (183.red-88-28-18.dynamicip.rima-tde.net. [88.28.18.183]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e969ddb85sm144106025e9.2.2024.09.30.02.11.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 02:11:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727687472; x=1728292272; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CFaQW0OfcXDNSv5OAJ0dPlLZ03IofsgYwsxu/4pf3Z8=; b=lToO5Kfym4rT5yZaBIJvwvtGs8bv0dTLG8Cf3euYrN/JUrjyp1C9xUUs9JpkiK1xUx UjCd1iSEW042XY8yJAf7q2jz0iwRjXtOpQSnfd3dEAgOJ8jYbBSqTtZST0woAit80jw2 7q0dY03kGZ1xoxPuS40CYwyN6RYwDG/ayzQWcpmwV4V67CtVCKH2BxXXf+N4wZfEsdMJ 3WyiojyZwD2QvZryES1/sClYFlsGrMQZn2bCRJojf+dvWdWsfLK6qr2K5FlSDx4GOFGb 9AZT8mCxgL9LQCon3v7AsixnEu7qAJA1Aql/sY2ytnhk/pb6fGHfs7/TtCosZlmDMEPR lL1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727687472; x=1728292272; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CFaQW0OfcXDNSv5OAJ0dPlLZ03IofsgYwsxu/4pf3Z8=; b=BxzceaqoAIWTJO4XnDj6Whc95Jlrn8jYacBcUL5SiQj30MwsNNEMe09JnW08wTZ693 zDCgbXqmKwY8XecQ8iXw6G7BCha9FL0+rFaFTJAn2HE9vYeQPeabeMtt8XuSi9ZXYrwJ Z2Q4ehAToUGI7wW/jRXEIpYoRUEiU/8lWEB70u9vhPepm+hwOxVHn5lSuunoPyWVc1Nz LZIqY8GL2O/x1uYYerjjpG/zBVvG5nnuQFjN+hKDXeEP2yB5Ww38pGNFsYP6bS7ZyHVu kruwhLUD8Aj3gOrV1o15YXmiPC0Lu/F2oIJzusvoz1JwbVOeMcT0gzWukYpebyiBSe+x S6Cw== X-Gm-Message-State: AOJu0YzGI0fVOaWwRp9WHouCYiy2gaaarFOEor+FV/9QkSlUZWg1Oyk/ 8QDAWtAXbRBQOLfLYvMsUzjBea3RE+w318DZ5BAwpRKmFUDMHSk5BpC8r/f9NJc42WiThLamuCA Z X-Google-Smtp-Source: AGHT+IEpq7EAXrM9chFNANAbCwVEd8GTqU43vv2HIljxflw96YCXEYGlw4eQsQGH/gSo3eUCxRcEOg== X-Received: by 2002:a05:600c:511a:b0:42c:b97a:5f7d with SMTP id 5b1f17b1804b1-42f5840cfd3mr92606615e9.7.1727687472033; Mon, 30 Sep 2024 02:11:12 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson Subject: [PATCH 01/12] target/mips: Declare cpu_is_bigendian_env() in 'internal.h' Date: Mon, 30 Sep 2024 11:10:50 +0200 Message-ID: <20240930091101.40591-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930091101.40591-1-philmd@linaro.org> References: <20240930091101.40591-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727687511242116600 In order to re-use cpu_is_bigendian(), declare it on "internal.h" after renaming it as cpu_is_bigendian_env(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/internal.h | 6 ++++++ target/mips/tcg/ldst_helper.c | 15 +++++---------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index a9a22ea00e..1ce2bbf62d 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -9,6 +9,7 @@ #define MIPS_INTERNAL_H =20 #include "exec/memattrs.h" +#include "exec/memop.h" #ifdef CONFIG_TCG #include "tcg/tcg-internal.h" #endif @@ -287,6 +288,11 @@ static inline int mips_vp_active(CPUMIPSState *env) return 1; } =20 +static inline bool cpu_is_bigendian_env(CPUMIPSState *env) +{ + return extract32(env->CP0_Config0, CP0C0_BE, 1); +} + static inline void compute_hflags(CPUMIPSState *env) { env->hflags &=3D ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index 97056d00a2..3d5cd2fdfa 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -53,11 +53,6 @@ HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong)) =20 #endif /* !CONFIG_USER_ONLY */ =20 -static inline bool cpu_is_bigendian(CPUMIPSState *env) -{ - return extract32(env->CP0_Config0, CP0C0_BE, 1); -} - static inline target_ulong get_lmask(CPUMIPSState *env, target_ulong value, unsigned bits) { @@ -65,7 +60,7 @@ static inline target_ulong get_lmask(CPUMIPSState *env, =20 value &=3D mask; =20 - if (!cpu_is_bigendian(env)) { + if (!cpu_is_bigendian_env(env)) { value ^=3D mask; } =20 @@ -76,7 +71,7 @@ void helper_swl(CPUMIPSState *env, target_ulong arg1, tar= get_ulong arg2, int mem_idx) { target_ulong lmask =3D get_lmask(env, arg2, 32); - int dir =3D cpu_is_bigendian(env) ? 1 : -1; + int dir =3D cpu_is_bigendian_env(env) ? 1 : -1; =20 cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); =20 @@ -100,7 +95,7 @@ void helper_swr(CPUMIPSState *env, target_ulong arg1, ta= rget_ulong arg2, int mem_idx) { target_ulong lmask =3D get_lmask(env, arg2, 32); - int dir =3D cpu_is_bigendian(env) ? 1 : -1; + int dir =3D cpu_is_bigendian_env(env) ? 1 : -1; =20 cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); =20 @@ -130,7 +125,7 @@ void helper_sdl(CPUMIPSState *env, target_ulong arg1, t= arget_ulong arg2, int mem_idx) { target_ulong lmask =3D get_lmask(env, arg2, 64); - int dir =3D cpu_is_bigendian(env) ? 1 : -1; + int dir =3D cpu_is_bigendian_env(env) ? 1 : -1; =20 cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); =20 @@ -174,7 +169,7 @@ void helper_sdr(CPUMIPSState *env, target_ulong arg1, t= arget_ulong arg2, int mem_idx) { target_ulong lmask =3D get_lmask(env, arg2, 64); - int dir =3D cpu_is_bigendian(env) ? 1 : -1; + int dir =3D cpu_is_bigendian_env(env) ? 1 : -1; =20 cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); =20 --=20 2.45.2 From nobody Sat Dec 21 15:47:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727687661; cv=none; d=zohomail.com; s=zohoarc; b=nggBePpbvQBXXd6nBFO0YD9zYejqEvAPcuosgmtb/l5EG7lYEKxwRn2ScpeWMQ2ZXzk18MQ87MEXL8DTmMfXhJ7AQV22ictGGE3TB2/OPhzwgcDu0vmenaU3hiZZ7wCxCORnmtCqKmgu4T6JsCMBRUigaQJ6m2fqhs82DpKYEGA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727687661; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gTfK1Y7AoteS474Co0RWkp3B9nFmF0nIHDb3RW7qOck=; b=YGIT4MbnLnBYyZItJASKFPzMK1BBstfe+pD4I8eKT7RbsCCMcPMmR97ieSv8RdhYfPfgL8ofROQsyaYUKt35COGwCXeOq5kN3REIxBwGhiA51fDw9RyoUEu2hEvFRCLdSn1Om1QOJprYr/yR2uYadMxogaG0ubvPeeQb1ojrLiw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727687661317282.27052509542295; Mon, 30 Sep 2024 02:14:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svCRA-0007m0-I0; Mon, 30 Sep 2024 05:11:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svCR8-0007ep-Gp for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:11:22 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svCR6-0004UL-Ty for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:11:22 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-37ce8458ae3so785137f8f.1 for ; Mon, 30 Sep 2024 02:11:20 -0700 (PDT) Received: from localhost.localdomain (183.red-88-28-18.dynamicip.rima-tde.net. [88.28.18.183]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd57429e5sm8486235f8f.98.2024.09.30.02.11.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 02:11:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727687479; x=1728292279; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gTfK1Y7AoteS474Co0RWkp3B9nFmF0nIHDb3RW7qOck=; b=H4BRA/NGY8u5uyAmg0L+UL0hiDkf3e75Lu6iPFJ0oYGSXV3j1cN9fLUbork1xJZTeo HY1mO5z24Q08Di1/Gd6+guYis1rrQpqpjj5xFWzmSrO/x2iKQ7D9fOH01Tk8JZrRIS8t /q6uB3SafbOjebHuhF0Ly5MLsiQQXlHKIVN6nA3QHbwkid57VvP6L8ztTovcq8yYBwTK 91BLFvsURauN02zSE8vdVu/Opy/hANoinvVzKSgd2IkpUkUa9fyfIUhdbWNWAOPR0zNB /Ub/uWvzb47NS+aFPitKOCm1MCUwVdBGpF6QKtBYJOgbdvnYnR1LOrV19y0FJuNashkc CFXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727687479; x=1728292279; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gTfK1Y7AoteS474Co0RWkp3B9nFmF0nIHDb3RW7qOck=; b=HPIH/RmpIBokBWXrjutVLNeT/R/mBr/M9/tcOgMhm8O+TfaLVDMrufrdoEh/ETmCli A8p5sYOYgfhS2ZpdVVg1NyPEVw72WpFVY3h3lC9QjvrDIMhgBDUpIid4DvafeNePMj3X vP/ucZ3eP23QgDL5aN8aRQh7TQ8Sid/QVzohrn67RymtHCjTFfSZPw6pDH0Y1hnPk44O WIWdPeJ533mxfzRQ59ep2Urh4HKNfbUUseTT9ExLnevqtHZppRwQPkL5tu5sL6RPF/1R /AM8BrvGoM60mcWdXUcf6WnYoDYM4e8XLQJT+k5yLfFGAZnnWdHeRFKGTY3mW8MvB/MS JKCA== X-Gm-Message-State: AOJu0Yx9HerL4EWtXnm4HsGpFZEIJnqRMqqq24cmU4e7wa9CDyu/SQ8Q vPBJsoxh81o0XHu0HNiRVz4oB0mOGNxGVG0TUv5F5a6NwlwSeF95PZhl6qBwrC5VjhRTUOsbcxq 7 X-Google-Smtp-Source: AGHT+IHLyDLMvH7R5jMc9L6T+pPt/e4XTSIzrVwfL5PG/fZEBYYRyWYqTKGotxGPWdA1evhWYP0TuA== X-Received: by 2002:a5d:4b8e:0:b0:37c:d123:f3bf with SMTP id ffacd0b85a97d-37cd5a69735mr11617422f8f.3.1727687478879; Mon, 30 Sep 2024 02:11:18 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson Subject: [PATCH 02/12] target/mips: Introduce mo_endian_env() helper Date: Mon, 30 Sep 2024 11:10:51 +0200 Message-ID: <20240930091101.40591-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930091101.40591-1-philmd@linaro.org> References: <20240930091101.40591-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727687663007116600 Introduce mo_endian_env() which returns the endian MemOp corresponding to the vCPU env. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/internal.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/mips/internal.h b/target/mips/internal.h index 1ce2bbf62d..5fe1af22ff 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -293,6 +293,11 @@ static inline bool cpu_is_bigendian_env(CPUMIPSState *= env) return extract32(env->CP0_Config0, CP0C0_BE, 1); } =20 +static inline MemOp mo_endian_env(CPUMIPSState *env) +{ + return cpu_is_bigendian_env(env) ? MO_BE : MO_LE; +} + static inline void compute_hflags(CPUMIPSState *env) { env->hflags &=3D ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | --=20 2.45.2 From nobody Sat Dec 21 15:47:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727687550; cv=none; d=zohomail.com; s=zohoarc; b=UkcRvNKP5t8ZnnNsS3A2pvLrLqdAalX8l+OXo1p4n1go0LlmdeePAaKRkNDEI33g6bx3VAs+iT8ykYhXmxzl7NeA6NQJ8psmPao2Yq+1iZEoawBEmcvCT0HvfHmFtxN1Zbw/uB1PPVnGs8PUrGkrJf379DhDKrorfsNDyEfDXrA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727687550; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7J2h8RAUijw3GDZwtE7CevTrntbSJ/9Vqd2w1TdBKEw=; b=f/qoDp2ac4no4GcLErHqjH2qfC6R9so/1ZJhE2z+TuiAYXEKRHq4OOtEeoZVimQ9VAxb9ULZZME/m88aiejDw8EPXYLclwQh/UdAVsO2iMwXvzQn/h0z5zSUa2fzZUAfMdKZ6/Ng3bDJ2kbjRf8wFxvFbcsn2PElNvMTSYtPow0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727687550117542.766980153297; Mon, 30 Sep 2024 02:12:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svCRG-00088W-Bu; Mon, 30 Sep 2024 05:11:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svCRF-00083q-7C for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:11:29 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svCRD-0004Uk-NG for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:11:28 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-42cacabd2e0so31443795e9.3 for ; Mon, 30 Sep 2024 02:11:27 -0700 (PDT) Received: from localhost.localdomain (183.red-88-28-18.dynamicip.rima-tde.net. [88.28.18.183]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd572fbd3sm8491315f8f.84.2024.09.30.02.11.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 02:11:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727687486; x=1728292286; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7J2h8RAUijw3GDZwtE7CevTrntbSJ/9Vqd2w1TdBKEw=; b=hnLLPfzN75iWkogIgLLcsCooPac4gZ3s89lXeXsXB7lMWlcrUxWDbG/xDrF3NvHuJN bq1eJdZnminePcEU1p6/FvyCHPOzfOHztbyXw0TEPQ4dkfKjY9s1SZpLf5bocODv040K qG8f/iOZRV9ARwJS2M21m5SqFX9TXJxkLpER0nXdLu4hrsDCVYMS7cI6YUztjlpoYPHx LoxHHHm+ZuuVNJ56LbJhLQ5qdM95Nj4pBOsfAdglJjNWJ6LUlGv/U7n/bKCC3lZaE6Tz tPUV5JVwBQoj68yBUzFSxrhlaROBQ70X3vNchCAnIV2kqY4I1RavkooaC8hrQVObKr8K ad3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727687486; x=1728292286; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7J2h8RAUijw3GDZwtE7CevTrntbSJ/9Vqd2w1TdBKEw=; b=XwBbAVuk8u0DH/Enq8UnQQ70Fcroau6YtZXyToJe6nDyeeeRzPQggebYSBzyNRDJHk Q20Nw7K2oCjMY6cIaigki9TB20z/P5Hl8rAOA1NqRY6GO77/D/5ODS2kcgOy1913+hVK mnHfOxW6Ng29EVV2Z/+VUOO/lrjRUXXz8yswIFRgq7piQ/RIuW/BBjC20fJVrUbYbFBl fn6ElRGMDaHk5jgj/5xyEfV/6qOqAZd2uAiPufM2Ujltz5RZfQJi9IPnR6FQrK4/RLKp 7BQhKt1d45L1gwF6eb5A5Z2fOFlCeqaS1ozF2ZMhtucrONoanCspiPvyq3XEc0EHopeB MmSw== X-Gm-Message-State: AOJu0Yz9vwgQhYSAz7C4Vge9EU8pagxDZhLAq2DA9c4LKz0Ga3EcfsBJ w6xPeVpusT26vsFybeu+JYcUAkxsGJjt8Ol3NihjDWHgm9NUZbNg/5tePIfJpVvUIaAMVnw9JdK G X-Google-Smtp-Source: AGHT+IE1D5DLEiqGfFJkDc7w2uq6H/S5D9fmXDMbbyWdjifsOpgM6pDADWkyDK3YiAIoYFbr61HKmQ== X-Received: by 2002:a05:600c:1912:b0:42c:b4f1:f2ad with SMTP id 5b1f17b1804b1-42f58497379mr83771775e9.33.1727687485866; Mon, 30 Sep 2024 02:11:25 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson Subject: [PATCH 03/12] target/mips: Replace MO_TE by mo_endian_env() in get_pte() Date: Mon, 30 Sep 2024 11:10:52 +0200 Message-ID: <20240930091101.40591-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930091101.40591-1-philmd@linaro.org> References: <20240930091101.40591-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727687551539116600 Replace compile-time MO_TE evaluation by runtime mo_endian_env() one, which expand target endianness from vCPU env. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/tcg/sysemu/tlb_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index 3836137750..e98bb95951 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -601,7 +601,7 @@ static bool get_pte(CPUMIPSState *env, uint64_t vaddr, = MemOp op, return false; } =20 - oi =3D make_memop_idx(op | MO_TE, ptw_mmu_idx); + oi =3D make_memop_idx(op | mo_endian_env(env), ptw_mmu_idx); if (op =3D=3D MO_64) { *pte =3D cpu_ldq_mmu(env, vaddr, oi, 0); } else { --=20 2.45.2 From nobody Sat Dec 21 15:47:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727687592; cv=none; d=zohomail.com; s=zohoarc; b=eJeIzByA7V0/OicCAjBPG23VbP12zwo0TjRfaDUWBEWIycXCnOC+wsya+rK/WkIymIiGJ45DSxuxwbnGBYO+Ays+BkCpJ+fEenoWK7B9K6tJZSNNs1HTmtV3oY5CRTnMdHlfILy4PCtvUBQ/un8XkYrCpk1koUrAuB5k+TP4wCg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727687592; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7QhDoekpFyldPlQdJYrNU9meNhoETaKUrN8Umy5eIAI=; b=c+7jLyMYNW7j6bDmKvRxeWPTpMIX0lifYuFGMyT385gGvHAdmblt3Udtl2CGFShFOsoDbO+hevh8vBNQTXqw0Wo2cwV0bPdyGyOy/nVWimh2/gVWG+IGu6slZEBsA0vT6fldhzfM0de+GfVDdB/ut6EUqNwcNXOcR3p9fFcoAfc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727687592050966.4422746570743; Mon, 30 Sep 2024 02:13:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svCRd-0000qs-DE; Mon, 30 Sep 2024 05:11:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svCRW-0000bW-FX for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:11:47 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svCRT-0004XP-IW for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:11:46 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-37cc810ce73so2354053f8f.1 for ; Mon, 30 Sep 2024 02:11:36 -0700 (PDT) Received: from localhost.localdomain (183.red-88-28-18.dynamicip.rima-tde.net. [88.28.18.183]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd55a5414sm8663530f8f.0.2024.09.30.02.11.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 02:11:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727687495; x=1728292295; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7QhDoekpFyldPlQdJYrNU9meNhoETaKUrN8Umy5eIAI=; b=ps1Jw4bWCezUraDLV9ca4l8aOhKBkFZdrSJPjvyw+jgNLj8Uexc7/kfoTxrWC5jvZZ 5nZvvobPC0u1Plm5RjNzLtAY2vcISxpBYHSn3wuVIsgJBVbYcHKKXum7flP57rV5U+Ck MqhHhpDbR3uB8B+cxwdg9NTHv/UqC5cyppI2Z6jypdbv4hbGrrb5s2P9VONIn+ybU1MO b52iGn/sT6dAgBIgyJndj444Ghfj87h0RYs79B1El2chYk5GysYaYeHw57zyOQ0k4f4R w0hxhgvI3HaFn64m0IEL/1qFENQKiMYrctOL5h5rjAfLbBdZXx5BW0dptoWWla8Ui3VS 29Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727687495; x=1728292295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7QhDoekpFyldPlQdJYrNU9meNhoETaKUrN8Umy5eIAI=; b=prPgDn4AKKQaEVMD4/1K8nc7pjjZnVRGeqABDngcWm9P+93ohRCFqsDEIgvhal1U49 BKV5PFPxkxetKrLRQqheKvIu/VA6EOcQb5b2p4BUbTzlrT8rVJJuIxKO0NqdHrDDgS2v pr/Ov0h/P2LtA90A7MVqKQ4ZGYSWdHeA+FL+GYKEvJ5XvX3v7ViTLW1REw6e/HDuO7UX qHcvc3aqF6rZH0r2N3Do/IkVf7q+yS/l0TLmp3GYST0Uh/cBNKG6f7OcAYLxej1MB8vt /wZ8gukJWd+/rBqIad3gqeUx2AjkVKRYBhFJeAzFXCU3ObaOoM+8ym7KtGtZp7XUORBp 7VsA== X-Gm-Message-State: AOJu0YzqfXyUX06lhmS7N4/vj47Pjccmtw9HNNrs9D8dv0e6JYQKX32x Il7rwY72+v982P8sj/onF9aN3ZFNPHLbMfe7L90OQ4+ue+R3W+Q0+8l86WRqJDcyuZvw7932kRU K X-Google-Smtp-Source: AGHT+IHbJZMtSvXM2rJRXIzWlyE59PFwfl7Z30loVoLD0QxJot3py644zZglOycwtv7X/LxoEpZqYw== X-Received: by 2002:adf:fec3:0:b0:37c:ca21:bc5d with SMTP id ffacd0b85a97d-37cd5aa9ab4mr5030789f8f.17.1727687494884; Mon, 30 Sep 2024 02:11:34 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson Subject: [PATCH 04/12] target/mips: Convert mips16e decr_and_load/store() macros to functions Date: Mon, 30 Sep 2024 11:10:53 +0200 Message-ID: <20240930091101.40591-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930091101.40591-1-philmd@linaro.org> References: <20240930091101.40591-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727687595059116600 Functions are easier to rework than macros. Besides, there is no gain here in inlining these. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Tested-by: Jiaxun Yang --- target/mips/tcg/mips16e_translate.c.inc | 101 +++++++++++++----------- 1 file changed, 53 insertions(+), 48 deletions(-) diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips= 16e_translate.c.inc index 5cffe0e412..31bc14f9ca 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -122,11 +122,23 @@ enum { =20 static int xlat(int r) { - static int map[] =3D { 16, 17, 2, 3, 4, 5, 6, 7 }; + static const int map[] =3D { 16, 17, 2, 3, 4, 5, 6, 7 }; =20 return map[r]; } =20 +static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0) +{ + TCGv t1 =3D tcg_temp_new(); + TCGv t2 =3D tcg_temp_new(); + + tcg_gen_movi_tl(t2, -4); + gen_op_addr_add(ctx, t0, t0, t2); + gen_load_gpr(t1, regidx); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); +} + static void gen_mips16_save(DisasContext *ctx, int xsregs, int aregs, int do_ra, int do_s0, int do_s1, @@ -196,46 +208,38 @@ static void gen_mips16_save(DisasContext *ctx, =20 gen_load_gpr(t0, 29); =20 -#define DECR_AND_STORE(reg) do { \ - tcg_gen_movi_tl(t2, -4); \ - gen_op_addr_add(ctx, t0, t0, t2); \ - gen_load_gpr(t1, reg); \ - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | \ - ctx->default_tcg_memop_mask); \ - } while (0) - if (do_ra) { - DECR_AND_STORE(31); + decr_and_store(ctx, 31, t0); } =20 switch (xsregs) { case 7: - DECR_AND_STORE(30); + decr_and_store(ctx, 30, t0); /* Fall through */ case 6: - DECR_AND_STORE(23); + decr_and_store(ctx, 23, t0); /* Fall through */ case 5: - DECR_AND_STORE(22); + decr_and_store(ctx, 22, t0); /* Fall through */ case 4: - DECR_AND_STORE(21); + decr_and_store(ctx, 21, t0); /* Fall through */ case 3: - DECR_AND_STORE(20); + decr_and_store(ctx, 20, t0); /* Fall through */ case 2: - DECR_AND_STORE(19); + decr_and_store(ctx, 19, t0); /* Fall through */ case 1: - DECR_AND_STORE(18); + decr_and_store(ctx, 18, t0); } =20 if (do_s1) { - DECR_AND_STORE(17); + decr_and_store(ctx, 17, t0); } if (do_s0) { - DECR_AND_STORE(16); + decr_and_store(ctx, 16, t0); } =20 switch (aregs) { @@ -270,23 +274,34 @@ static void gen_mips16_save(DisasContext *ctx, } =20 if (astatic > 0) { - DECR_AND_STORE(7); + decr_and_store(ctx, 7, t0); if (astatic > 1) { - DECR_AND_STORE(6); + decr_and_store(ctx, 6, t0); if (astatic > 2) { - DECR_AND_STORE(5); + decr_and_store(ctx, 5, t0); if (astatic > 3) { - DECR_AND_STORE(4); + decr_and_store(ctx, 4, t0); } } } } -#undef DECR_AND_STORE =20 tcg_gen_movi_tl(t2, -framesize); gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2); } =20 +static void decr_and_load(DisasContext *ctx, unsigned regidx, TCGv t0) +{ + TCGv t1 =3D tcg_temp_new(); + TCGv t2 =3D tcg_temp_new(); + + tcg_gen_movi_tl(t2, -4); + gen_op_addr_add(ctx, t0, t0, t2); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | + ctx->default_tcg_memop_mask); + gen_store_gpr(t1, regidx); +} + static void gen_mips16_restore(DisasContext *ctx, int xsregs, int aregs, int do_ra, int do_s0, int do_s1, @@ -294,52 +309,43 @@ static void gen_mips16_restore(DisasContext *ctx, { int astatic; TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); TCGv t2 =3D tcg_temp_new(); =20 tcg_gen_movi_tl(t2, framesize); gen_op_addr_add(ctx, t0, cpu_gpr[29], t2); =20 -#define DECR_AND_LOAD(reg) do { \ - tcg_gen_movi_tl(t2, -4); \ - gen_op_addr_add(ctx, t0, t0, t2); \ - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | \ - ctx->default_tcg_memop_mask); \ - gen_store_gpr(t1, reg); \ - } while (0) - if (do_ra) { - DECR_AND_LOAD(31); + decr_and_load(ctx, 31, t0); } =20 switch (xsregs) { case 7: - DECR_AND_LOAD(30); + decr_and_load(ctx, 30, t0); /* Fall through */ case 6: - DECR_AND_LOAD(23); + decr_and_load(ctx, 23, t0); /* Fall through */ case 5: - DECR_AND_LOAD(22); + decr_and_load(ctx, 22, t0); /* Fall through */ case 4: - DECR_AND_LOAD(21); + decr_and_load(ctx, 21, t0); /* Fall through */ case 3: - DECR_AND_LOAD(20); + decr_and_load(ctx, 20, t0); /* Fall through */ case 2: - DECR_AND_LOAD(19); + decr_and_load(ctx, 19, t0); /* Fall through */ case 1: - DECR_AND_LOAD(18); + decr_and_load(ctx, 18, t0); } =20 if (do_s1) { - DECR_AND_LOAD(17); + decr_and_load(ctx, 17, t0); } if (do_s0) { - DECR_AND_LOAD(16); + decr_and_load(ctx, 16, t0); } =20 switch (aregs) { @@ -374,18 +380,17 @@ static void gen_mips16_restore(DisasContext *ctx, } =20 if (astatic > 0) { - DECR_AND_LOAD(7); + decr_and_load(ctx, 7, t0); if (astatic > 1) { - DECR_AND_LOAD(6); + decr_and_load(ctx, 6, t0); if (astatic > 2) { - DECR_AND_LOAD(5); + decr_and_load(ctx, 5, t0); if (astatic > 3) { - DECR_AND_LOAD(4); + decr_and_load(ctx, 4, t0); } } } } -#undef DECR_AND_LOAD =20 tcg_gen_movi_tl(t2, framesize); gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2); --=20 2.45.2 From nobody Sat Dec 21 15:47:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727687549; cv=none; d=zohomail.com; s=zohoarc; b=Nbo81ilPyJyxAzCeYU0WIcweD8FG9cEmCK2OThjMuHKmHoR1D1848aTLnDmQQd1lV/wWrCjPlb+IgrNia2gJ/Nc0FipBk3vJAHssahpb8jKDPQKAadZ/fJBF/ObDcI7Q4vmhGy8JuXtZyRAD+RQ7LFKLUbgAWm/4mSDgI9ccxxw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727687549; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8CVXM7w3ItHRS1f3yj+MesBCV77dY6lwF6BVY6QS2jI=; b=RYXic+VrJtmEmSLNm0Jriak7XCCezWphisN31k8r4rVMI3rdNosRcGhXLJF2iqmlnjmKO/na1QnVRE9mhSJZPlo/AcumufnKpIqj61McPEx/h9sclgBP4H2Fh9WBXnEv9K3r+KZs+O6eUhO8el3StF2BDniZ8DqjcSr9nLGO63k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727687549788244.52851074987882; Mon, 30 Sep 2024 02:12:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svCRb-0000he-Sz; Mon, 30 Sep 2024 05:11:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svCRW-0000b8-9p for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:11:46 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svCRU-0004Xx-67 for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:11:46 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-42cbface8d6so51089695e9.3 for ; Mon, 30 Sep 2024 02:11:43 -0700 (PDT) Received: from localhost.localdomain (183.red-88-28-18.dynamicip.rima-tde.net. [88.28.18.183]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd56e8822sm8572863f8f.50.2024.09.30.02.11.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 02:11:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727687502; x=1728292302; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8CVXM7w3ItHRS1f3yj+MesBCV77dY6lwF6BVY6QS2jI=; b=BgoyjkAaEt7a5wggprWcAPqNbOxHZJMtg5dJgiNBrEvByTTxuc9ck6jYqXHWq4vIqw Szz/BMIegoaF2is1Dnt5YrU/GEaHvrtjmbVWzrte6+Ysw1OOQI5RjZu32Aqrfx+d7W6Q RhGYJI9cI5q4DLNWiC3uOOScL5Vg8Mo11eozsoRMbf1lR9XKc0qSkH3WDU1xPDG/SlU/ VGO9omdPAdcmCOLYzPDHNXXp20jCFt0YVxZ+bhonuBHyJLjmrGoE+03IJo9VK6J3Wtfu 7sl8qHMw25bocHS/H7bsfOxhI38W+isOkbU5uzqMJtcR1qK2bXV7939vWt+yUgNKPXXN jZMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727687502; x=1728292302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8CVXM7w3ItHRS1f3yj+MesBCV77dY6lwF6BVY6QS2jI=; b=F4pPeTAuoZbPb4TnISKAZvaDznEmX14jdO7vJrwHXn1dIG9Er9hh7ckYlIMdTICc1A 8RNKY0C7R9SUxJmC8s4sfQMLZkREQSt+eNIFry8ssNHpX0ssNuMqagpdNyy5mJDw0CIT hUisGyrMozAIVsmxOHjS0NAxkxwoTaRiOQvjNqDrn1h+C9SPzp/MKEZkaV79fs1KKyGq f5C0+iA8TmrgIVNhoCdQRSHZvtvkxJ+7mQ7TubVpbMX711OC2Y4+Ck+J7AOSXDc/LSjM 9ZSw+iu0ujTJjAk1qLTgnRBjC54SJp3TQ9VoOj82BKgauWXJcpYFWsOBAXGTuCwN/J3Z 1HIg== X-Gm-Message-State: AOJu0YzpdWKnU9WpgeMZdjS/MfaluShmh0gdUVG206CWGRPGNBnbYeaj QKsXsSq9y5jcr0YNa6xcV70hCzhTxjR0acJLFdNdwjPpzBicKrBUi6GQxSQ2b9Ep3JfhV/7EWYc W X-Google-Smtp-Source: AGHT+IHtiSufjhOEkxb6X6U2Pim46ybmDAGhY9KoqDYmOKrtCyKo1QHyweB4o4obH+kaIlCsfv27Qg== X-Received: by 2002:a5d:574b:0:b0:37c:cf1a:b2a8 with SMTP id ffacd0b85a97d-37cd59def87mr10654824f8f.0.1727687501970; Mon, 30 Sep 2024 02:11:41 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson Subject: [PATCH 05/12] target/mips: Introduce mo_endian() helper Date: Mon, 30 Sep 2024 11:10:54 +0200 Message-ID: <20240930091101.40591-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930091101.40591-1-philmd@linaro.org> References: <20240930091101.40591-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727687551534116600 Introduce mo_endian() which returns the endian MemOp corresponding to the vCPU DisasContext. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/tcg/translate.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 2b6646b339..54955437ef 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -240,4 +240,9 @@ static inline bool cpu_is_bigendian(DisasContext *ctx) return extract32(ctx->CP0_Config0, CP0C0_BE, 1); } =20 +static inline MemOp mo_endian(DisasContext *dc) +{ + return cpu_is_bigendian(dc) ? MO_BE : MO_LE; +} + #endif --=20 2.45.2 From nobody Sat Dec 21 15:47:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727687553; cv=none; d=zohomail.com; s=zohoarc; b=DR9wgRtvqXxxNfXR2FY/3bR8Z6G0qeiLYY5AcUb+RX+p7swJFbcjdQJ2XzcQiwVTp2d5jd+Lhj3TgxmXrohP82Y0Dl+U8RW4cbom7/C11s/N4x3xCiT0zK4giyRvoO1v+LQNTt/cKlCScsIVZfVSklgyFBqyMeCf72ppEzt+k8s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727687553; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xe8ibOwFnRIMlTGImGSanb0hSlMbHwC9x9mAJ2BGppM=; b=W9TYetOBrElWMKDfIH1QEdFoZcSJOMV7lyVt7O6n9j5QPnLYdZm65/f8MLvVz2mJxFDaMjPlUq82VwNr6mAk0TU3SYWQuF2E58X9m8Tqx4WVVTVTKPjSonTuhUinoL6xhk735ac/sQLW0rK8blgdN0OqzruPduzD77lpG3wIDFA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727687553216296.07066534207706; Mon, 30 Sep 2024 02:12:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svCRh-0001Cj-5n; Mon, 30 Sep 2024 05:11:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svCRf-000175-Va for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:11:56 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svCRc-0004bT-0s for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:11:55 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-42e7b7bef42so32920925e9.3 for ; Mon, 30 Sep 2024 02:11:51 -0700 (PDT) Received: from localhost.localdomain (183.red-88-28-18.dynamicip.rima-tde.net. [88.28.18.183]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd574283fsm8461586f8f.99.2024.09.30.02.11.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 02:11:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727687510; x=1728292310; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xe8ibOwFnRIMlTGImGSanb0hSlMbHwC9x9mAJ2BGppM=; b=mKjz6LLisjt4YvaHNa9IFZ5ytZnPnOWmox/ILQaaqD4a8q7SmN2Laq1NOX2Xt9fQrl +WVuYPP1Ib7QMQXfafeKjI04x/mx14jVivelWE6xouKnJXbUHx8m4GH7QabrL8hBjX7L 4rs7f0+hHUoN3Po2D1VxXuWQzDo3uW55j6JnA3wDWMfe/tNhcST4VmpUNs7lPtRrbCd0 oJ/m0+uBhYJiF2j2UnMci/i9d/uW1kdPZ8YxzTXHulIRuKI50KM/tOGPqmlDylIrFA6D Kk7oBDO0Gb4i5SG4b5cJjzsbmBVH3ax5gSgIIx8XHngSoUGO0Pf+sPU3AOre8VcxAwON brBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727687510; x=1728292310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xe8ibOwFnRIMlTGImGSanb0hSlMbHwC9x9mAJ2BGppM=; b=Axhsp/DVuRl04ekXNUrzQvfeDiNynQWWHuZxinRPtzMF3inXvtkwi6raatJwAeXpfI OuINu6rrklu/d36lno+JEIjXxRLqEtpTdk+WPOwK3XdxqiYPVVXa6T0l2ETELEMPeUam yS7CV8BLB/1GzxVXB1b9APh2LZ1B769mGNv1Ve7Y1asORc+QRmSPyWbcg8vJR7k1nKg6 ZJqOr5wr4MhhZPIdOVCNHC+lSdAkBrsk2EEOjCr1o+/8yQMMzwjmqA2brRisy86CRqw+ cM33kUTDr4omWMEXK79PWgMOnMkzPFDOYFcAlKYCaWWJ3HRuHEL0s1bre241N7rRs+M2 sjCA== X-Gm-Message-State: AOJu0YzyaEdnGLhuhREcLKrhUn9ElsHl5mqmMjj4DRPv767XHUDkC86v kkYNU+UUKy5E7x6mgCmT7VIWFnfIBFDgvhUGhNDHFcfZsmcsiiwq4DVTF1HsmLBggtZ8zTbYr/e 3 X-Google-Smtp-Source: AGHT+IG2cpwsQI6ArbE4zdMXjSxuk6MBofjxxCfvW7USVey60zomP5T/EnLb0sqGzU+r0uuMzFAvzg== X-Received: by 2002:a5d:49c2:0:b0:37c:d26c:8dc4 with SMTP id ffacd0b85a97d-37cd5af25cemr6166634f8f.36.1727687509701; Mon, 30 Sep 2024 02:11:49 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson Subject: [PATCH 06/12] target/mips: Explode MO_TExx -> MO_TE | MO_xx Date: Mon, 30 Sep 2024 11:10:55 +0200 Message-ID: <20240930091101.40591-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930091101.40591-1-philmd@linaro.org> References: <20240930091101.40591-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727687554963116600 Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/mips); \ done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/tcg/mxu_translate.c | 8 +- target/mips/tcg/translate.c | 120 +++++++++++----------- target/mips/tcg/tx79_translate.c | 8 +- target/mips/tcg/micromips_translate.c.inc | 22 ++-- target/mips/tcg/mips16e_translate.c.inc | 12 +-- target/mips/tcg/nanomips_translate.c.inc | 32 +++--- 6 files changed, 101 insertions(+), 101 deletions(-) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translat= e.c index c517258ac5..b221f7a4a0 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -1533,7 +1533,7 @@ static void gen_mxu_s32ldxx(DisasContext *ctx, bool r= eversed, bool postinc) tcg_gen_add_tl(t0, t0, t1); =20 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, - (MO_TESL ^ (reversed ? MO_BSWAP : 0)) | + (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) | ctx->default_tcg_memop_mask); gen_store_mxu_gpr(t1, XRa); =20 @@ -1569,7 +1569,7 @@ static void gen_mxu_s32stxx(DisasContext *ctx, bool r= eversed, bool postinc) =20 gen_load_mxu_gpr(t1, XRa); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - (MO_TESL ^ (reversed ? MO_BSWAP : 0)) | + (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) | ctx->default_tcg_memop_mask); =20 if (postinc) { @@ -1605,7 +1605,7 @@ static void gen_mxu_s32ldxvx(DisasContext *ctx, bool = reversed, tcg_gen_add_tl(t0, t0, t1); =20 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, - (MO_TESL ^ (reversed ? MO_BSWAP : 0)) | + (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) | ctx->default_tcg_memop_mask); gen_store_mxu_gpr(t1, XRa); =20 @@ -1675,7 +1675,7 @@ static void gen_mxu_s32stxvx(DisasContext *ctx, bool = reversed, =20 gen_load_mxu_gpr(t1, XRa); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - (MO_TESL ^ (reversed ? MO_BSWAP : 0)) | + (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) | ctx->default_tcg_memop_mask); =20 if (postinc) { diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 333469b268..906fd3d73c 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1964,9 +1964,9 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, = int mem_idx, \ gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); = \ } #endif -OP_LD_ATOMIC(ll, MO_TESL); +OP_LD_ATOMIC(ll, MO_TE | MO_SL); #if defined(TARGET_MIPS64) -OP_LD_ATOMIC(lld, MO_TEUQ); +OP_LD_ATOMIC(lld, MO_TE | MO_UQ); #endif #undef OP_LD_ATOMIC =20 @@ -2073,12 +2073,12 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, switch (opc) { #if defined(TARGET_MIPS64) case OPC_LWU: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; case OPC_LD: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2090,33 +2090,33 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, case OPC_LDL: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxl(ctx, t1, t0, mem_idx, MO_TEUQ); + gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UQ); gen_store_gpr(t1, rt); break; case OPC_LDR: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxr(ctx, t1, t0, mem_idx, MO_TEUQ); + gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UQ); gen_store_gpr(t1, rt); break; case OPC_LDPC: t1 =3D tcg_constant_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ); gen_store_gpr(t0, rt); break; #endif case OPC_LWPC: t1 =3D tcg_constant_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL); + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL); gen_store_gpr(t0, rt); break; case OPC_LWE: mem_idx =3D MIPS_HFLAG_UM; /* fall through */ case OPC_LW: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2124,7 +2124,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, mem_idx =3D MIPS_HFLAG_UM; /* fall through */ case OPC_LH: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESW | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2132,7 +2132,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, mem_idx =3D MIPS_HFLAG_UM; /* fall through */ case OPC_LHU: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUW | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2156,7 +2156,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, case OPC_LWL: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxl(ctx, t1, t0, mem_idx, MO_TEUL); + gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UL); tcg_gen_ext32s_tl(t1, t1); gen_store_gpr(t1, rt); break; @@ -2166,7 +2166,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, case OPC_LWR: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxr(ctx, t1, t0, mem_idx, MO_TEUL); + gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UL); tcg_gen_ext32s_tl(t1, t1); gen_store_gpr(t1, rt); break; @@ -2194,7 +2194,7 @@ static void gen_st(DisasContext *ctx, uint32_t opc, i= nt rt, switch (opc) { #if defined(TARGET_MIPS64) case OPC_SD: - tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); break; case OPC_SDL: @@ -2208,14 +2208,14 @@ static void gen_st(DisasContext *ctx, uint32_t opc,= int rt, mem_idx =3D MIPS_HFLAG_UM; /* fall through */ case OPC_SW: - tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); break; case OPC_SHE: mem_idx =3D MIPS_HFLAG_UM; /* fall through */ case OPC_SH: - tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUW | + tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UW | ctx->default_tcg_memop_mask); break; case OPC_SBE: @@ -2281,7 +2281,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t = opc, int ft, case OPC_LWC1: { TCGv_i32 fp0 =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | + tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_fpr32(ctx, fp0, ft); } @@ -2290,14 +2290,14 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_= t opc, int ft, { TCGv_i32 fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, ft); - tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); } break; case OPC_LDC1: { TCGv_i64 fp0 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, fp0, ft); } @@ -2306,7 +2306,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t = opc, int ft, { TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, ft); - tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); } break; @@ -2987,14 +2987,14 @@ static inline void gen_pcrel(DisasContext *ctx, int= opc, target_ulong pc, case R6_OPC_LWPC: offset =3D sextract32(ctx->opcode << 2, 0, 21); addr =3D addr_add(ctx, pc, offset); - gen_r6_ld(addr, rs, ctx->mem_idx, MO_TESL); + gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_SL); break; #if defined(TARGET_MIPS64) case OPC_LWUPC: check_mips_64(ctx); offset =3D sextract32(ctx->opcode << 2, 0, 21); addr =3D addr_add(ctx, pc, offset); - gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUL); + gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UL); break; #endif default: @@ -3021,7 +3021,7 @@ static inline void gen_pcrel(DisasContext *ctx, int o= pc, target_ulong pc, check_mips_64(ctx); offset =3D sextract32(ctx->opcode << 3, 0, 21); addr =3D addr_add(ctx, (pc & ~0x7), offset); - gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUQ); + gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UQ); break; #endif default: @@ -4160,10 +4160,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, i= nt rt, case OPC_GSLQ: t1 =3D tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rt); gen_store_gpr(t0, lsq_rt1); @@ -4172,10 +4172,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, i= nt rt, check_cp1_enabled(ctx); t1 =3D tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, t1, rt); gen_store_fpr64(ctx, t0, lsq_rt1); @@ -4184,11 +4184,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, i= nt rt, t1 =3D tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); gen_load_gpr(t1, lsq_rt1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); break; case OPC_GSSQC1: @@ -4196,11 +4196,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, i= nt rt, t1 =3D tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); gen_load_fpr64(ctx, t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); gen_load_fpr64(ctx, t1, lsq_rt1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); break; #endif @@ -4213,7 +4213,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_load_fpr32(ctx, fp0, rt); t1 =3D tcg_temp_new(); tcg_gen_ext_i32_tl(t1, fp0); - gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUL); + gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL); tcg_gen_trunc_tl_i32(fp0, t1); gen_store_fpr32(ctx, fp0, rt); break; @@ -4224,7 +4224,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_load_fpr32(ctx, fp0, rt); t1 =3D tcg_temp_new(); tcg_gen_ext_i32_tl(t1, fp0); - gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUL); + gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL); tcg_gen_trunc_tl_i32(fp0, t1); gen_store_fpr32(ctx, fp0, rt); break; @@ -4234,7 +4234,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_base_offset_addr(ctx, t0, rs, shf_offset); t1 =3D tcg_temp_new(); gen_load_fpr64(ctx, t1, rt); - gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUQ); + gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ); gen_store_fpr64(ctx, t1, rt); break; case OPC_GSLDRC1: @@ -4242,7 +4242,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_base_offset_addr(ctx, t0, rs, shf_offset); t1 =3D tcg_temp_new(); gen_load_fpr64(ctx, t1, rt); - gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUQ); + gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ); gen_store_fpr64(ctx, t1, rt); break; #endif @@ -4360,7 +4360,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, gen_store_gpr(t0, rt); break; case OPC_GSLHX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -4369,7 +4369,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, if (rd) { gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -4379,7 +4379,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, if (rd) { gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -4390,7 +4390,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } fp0 =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | + tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_fpr32(ctx, fp0, rt); break; @@ -4400,7 +4400,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, if (rd) { gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, t0, rt); break; @@ -4413,34 +4413,34 @@ static void gen_loongson_lsdc2(DisasContext *ctx, i= nt rt, case OPC_GSSHX: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UW | ctx->default_tcg_memop_mask); break; case OPC_GSSWX: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); break; #if defined(TARGET_MIPS64) case OPC_GSSDX: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); break; #endif case OPC_GSSWXC1: fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, rt); - tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); break; #if defined(TARGET_MIPS64) case OPC_GSSDXC1: t1 =3D tcg_temp_new(); gen_load_fpr64(ctx, t1, rt); - tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); break; #endif @@ -10779,7 +10779,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, { TCGv_i32 fp0 =3D tcg_temp_new_i32(); =20 - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL); tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32(ctx, fp0, fd); } @@ -10789,7 +10789,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, check_cp1_registers(ctx, fd); { TCGv_i64 fp0 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10799,7 +10799,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, { TCGv_i64 fp0 =3D tcg_temp_new_i64(); =20 - tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10808,7 +10808,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, { TCGv_i32 fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); - tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL); + tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL); } break; case OPC_SDXC1: @@ -10817,7 +10817,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, { TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); } break; case OPC_SUXC1: @@ -10826,7 +10826,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, { TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); } break; } @@ -11476,7 +11476,7 @@ void gen_ldxs(DisasContext *ctx, int base, int inde= x, int rd) gen_op_addr_add(ctx, t0, t1, t0); } =20 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL); gen_store_gpr(t1, rd); } =20 @@ -11567,16 +11567,16 @@ static void gen_mips_lx(DisasContext *ctx, uint32= _t opc, gen_store_gpr(t0, rd); break; case OPC_LHX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW); gen_store_gpr(t0, rd); break; case OPC_LWX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL); gen_store_gpr(t0, rd); break; #if defined(TARGET_MIPS64) case OPC_LDX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ); gen_store_gpr(t0, rd); break; #endif @@ -13719,7 +13719,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) } break; case R6_OPC_SC: - gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); + gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false); break; case R6_OPC_LL: gen_ld(ctx, op1, rt, rs, imm); @@ -13765,7 +13765,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) #endif #if defined(TARGET_MIPS64) case R6_OPC_SCD: - gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false); + gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false); break; case R6_OPC_LLD: gen_ld(ctx, op1, rt, rs, imm); @@ -14448,7 +14448,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) return; case OPC_SCE: check_cp0_enabled(ctx); - gen_st_cond(ctx, rt, rs, imm, MO_TESL, true); + gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, true); return; case OPC_CACHEE: check_eva(ctx); @@ -14912,7 +14912,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); } - gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); + gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false); break; case OPC_CACHE: check_cp0_enabled(ctx); @@ -15191,7 +15191,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) check_insn_opc_user_only(ctx, INSN_R5900); } check_mips_64(ctx); - gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false); + gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false); break; case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */ if (ctx->insn_flags & ISA_MIPS_R6) { diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_transl= ate.c index dd6fb8a7bd..1d290b86a9 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -340,12 +340,12 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a) tcg_gen_andi_tl(addr, addr, ~0xf); =20 /* Lower half */ - tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); gen_store_gpr(t0, a->rt); =20 /* Upper half */ tcg_gen_addi_i64(addr, addr, 8); - tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); gen_store_gpr_hi(t0, a->rt); return true; } @@ -364,12 +364,12 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a) =20 /* Lower half */ gen_load_gpr(t0, a->rt); - tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); =20 /* Upper half */ tcg_gen_addi_i64(addr, addr, 8); gen_load_gpr_hi(t0, a->rt); - tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); return true; } =20 diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/mi= cromips_translate.c.inc index 7510831701..343d64a0e8 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -977,23 +977,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t= opc, int rd, gen_reserved_instruction(ctx); return; } - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 4); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd + 1); break; case SWP: gen_load_gpr(t1, rd); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); tcg_gen_movi_tl(t1, 4); gen_op_addr_add(ctx, t0, t0, t1); gen_load_gpr(t1, rd + 1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); break; #ifdef TARGET_MIPS64 @@ -1002,23 +1002,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32= _t opc, int rd, gen_reserved_instruction(ctx); return; } - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 8); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd + 1); break; case SDP: gen_load_gpr(t1, rd); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); tcg_gen_movi_tl(t1, 8); gen_op_addr_add(ctx, t0, t0, t1); gen_load_gpr(t1, rd + 1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); break; #endif @@ -2572,13 +2572,13 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_st(ctx, mips32_op, rt, rs, offset); break; case SC: - gen_st_cond(ctx, rt, rs, offset, MO_TESL, false); + gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, false); break; #if defined(TARGET_MIPS64) case SCD: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_st_cond(ctx, rt, rs, offset, MO_TEUQ, false); + gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_UQ, false); break; #endif case LD_EVA: @@ -2659,7 +2659,7 @@ static void decode_micromips32_opc(CPUMIPSState *env,= DisasContext *ctx) mips32_op =3D OPC_SHE; goto do_st_lr; case SCE: - gen_st_cond(ctx, rt, rs, offset, MO_TESL, true); + gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, true); break; case SWE: mips32_op =3D OPC_SWE; diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips= 16e_translate.c.inc index 31bc14f9ca..9dd867fe89 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -135,7 +135,7 @@ static void decr_and_store(DisasContext *ctx, unsigned = regidx, TCGv t0) tcg_gen_movi_tl(t2, -4); gen_op_addr_add(ctx, t0, t0, t2); gen_load_gpr(t1, regidx); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); } =20 @@ -184,25 +184,25 @@ static void gen_mips16_save(DisasContext *ctx, case 4: gen_base_offset_addr(ctx, t0, 29, 12); gen_load_gpr(t1, 7); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); /* Fall through */ case 3: gen_base_offset_addr(ctx, t0, 29, 8); gen_load_gpr(t1, 6); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); /* Fall through */ case 2: gen_base_offset_addr(ctx, t0, 29, 4); gen_load_gpr(t1, 5); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); /* Fall through */ case 1: gen_base_offset_addr(ctx, t0, 29, 0); gen_load_gpr(t1, 4); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); } =20 @@ -297,7 +297,7 @@ static void decr_and_load(DisasContext *ctx, unsigned r= egidx, TCGv t0) =20 tcg_gen_movi_tl(t2, -4); gen_op_addr_add(ctx, t0, t0, t2); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t1, regidx); } diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nan= omips_translate.c.inc index b4b746d418..40ef0346a7 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -998,7 +998,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, = int16_t offset, TCGv tmp2 =3D tcg_temp_new(); =20 gen_base_offset_addr(ctx, taddr, base, offset); - tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ | MO_ALIGN); + tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TE | MO_UQ | MO_ALIG= N); if (cpu_is_bigendian(ctx)) { tcg_gen_extr_i64_tl(tmp2, tmp1, tval); } else { @@ -1075,7 +1075,7 @@ static void gen_save(DisasContext *ctx, uint8_t rt, u= int8_t count, gen_base_offset_addr(ctx, va, 29, this_offset); gen_load_gpr(t0, this_rt); tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx, - (MO_TEUL | ctx->default_tcg_memop_mask)); + (MO_TE | MO_UL | ctx->default_tcg_memop_mask)); counter++; } =20 @@ -1095,7 +1095,7 @@ static void gen_restore(DisasContext *ctx, uint8_t rt= , uint8_t count, int this_rt =3D use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f= ); int this_offset =3D u - ((counter + 1) << 2); gen_base_offset_addr(ctx, va, 29, this_offset); - tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TESL | + tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); tcg_gen_ext32s_tl(t0, t0); gen_store_gpr(t0, this_rt); @@ -2647,13 +2647,13 @@ static void gen_p_lsx(DisasContext *ctx, int rd, in= t rs, int rt) case NM_LHX: /*case NM_LHXS:*/ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TESW | ctx->default_tcg_memop_mask); + MO_TE | MO_SW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rd); break; case NM_LWX: /*case NM_LWXS:*/ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TESL | ctx->default_tcg_memop_mask); + MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rd); break; case NM_LBUX: @@ -2663,7 +2663,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int = rs, int rt) case NM_LHUX: /*case NM_LHUXS:*/ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TEUW | ctx->default_tcg_memop_mask); + MO_TE | MO_UW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rd); break; case NM_SBX: @@ -2676,14 +2676,14 @@ static void gen_p_lsx(DisasContext *ctx, int rd, in= t rs, int rt) check_nms(ctx); gen_load_gpr(t1, rd); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_TEUW | ctx->default_tcg_memop_mask); + MO_TE | MO_UW | ctx->default_tcg_memop_mask); break; case NM_SWX: /*case NM_SWXS:*/ check_nms(ctx); gen_load_gpr(t1, rd); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_TEUL | ctx->default_tcg_memop_mask); + MO_TE | MO_UL | ctx->default_tcg_memop_mask); break; case NM_LWC1X: /*case NM_LWC1XS:*/ @@ -3737,7 +3737,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) =20 tcg_gen_movi_tl(t0, addr); tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, - MO_TESL | ctx->default_tcg_memop_ma= sk); + MO_TE | MO_SL | ctx->default_tcg_me= mop_mask); } break; case NM_SWPC48: @@ -3754,7 +3754,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_load_gpr(t1, rt); =20 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_TEUL | ctx->default_tcg_memop_ma= sk); + MO_TE | MO_UL | ctx->default_tcg_me= mop_mask); } break; default: @@ -4132,13 +4132,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) =20 switch (extract32(ctx->opcode, 11, 4)) { case NM_UALH: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE= SW | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE= | MO_SW | MO_UNALN); gen_store_gpr(t0, rt); break; case NM_UASH: gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE= UW | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE= | MO_UW | MO_UNALN); break; } @@ -4161,7 +4161,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) case NM_P_SC: switch (ctx->opcode & 0x03) { case NM_SC: - gen_st_cond(ctx, rt, rs, s, MO_TESL, false); + gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, false); break; case NM_SCWP: check_xnp(ctx); @@ -4274,7 +4274,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) check_xnp(ctx); check_eva(ctx); check_cp0_enabled(ctx); - gen_st_cond(ctx, rt, rs, s, MO_TESL, true); + gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, true); break; case NM_SCWPE: check_xnp(ctx); @@ -4317,7 +4317,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) switch (extract32(ctx->opcode, 11, 1)) { case NM_LWM: tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx, - memop | MO_TESL); + memop | MO_TE | MO_SL); gen_store_gpr(t1, this_rt); if ((this_rt =3D=3D rs) && (counter !=3D (count - 1))) { @@ -4328,7 +4328,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) this_rt =3D (rt =3D=3D 0) ? 0 : this_rt; gen_load_gpr(t1, this_rt); tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx, - memop | MO_TEUL); + memop | MO_TE | MO_UL); break; } counter++; --=20 2.45.2 From nobody Sat Dec 21 15:47:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727687630; cv=none; d=zohomail.com; s=zohoarc; b=S+eiPqq0ECJpbgyiICA9HPmY1Guw+Y0uVMZzAqc7ljCZEpKw6c+GDmWkZaSJkGTCIkIKUk4RfXoE358JvkCC5sPDl5SAAcsVvLT7fA8gHggUz3Nzgrx+zRK2aU1RvoWA2XMHiNTyIZOl33GWWpS1X0bNrEtqN+XW7fNX0hM+DHg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727687630; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Q7rvccsh9aj83xuH88lWH8I7b7DG49roHC3cpFazkmA=; b=m9pacGaXoKuZ9iH3WGF2NteHs74oNpbNauiaWnCpMIl4U11MSvgmIsebC5HqfdS3NqFptKT3i/26b9Xab6UanScajsvHF7iA0yBsma0ywgiFGtT3McTfhNlMabChXuXUVB2bLJzRR1d3j1fdOb3y1Tjmg5+haxgLHe5ontM8Xiw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727687630326117.9303583466716; Mon, 30 Sep 2024 02:13:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svCRq-00026m-Ln; Mon, 30 Sep 2024 05:12:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svCRn-0001uP-EV for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:12:03 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svCRj-0004d8-AS for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:12:03 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-37cc846fbc4so2904956f8f.2 for ; Mon, 30 Sep 2024 02:11:58 -0700 (PDT) Received: from localhost.localdomain (183.red-88-28-18.dynamicip.rima-tde.net. [88.28.18.183]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd57429e5sm8487425f8f.98.2024.09.30.02.11.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 02:11:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727687517; x=1728292317; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q7rvccsh9aj83xuH88lWH8I7b7DG49roHC3cpFazkmA=; b=Jz7qazkOxrbeHIk4pkV7oZh0l637IE8iXQ7wCK7gxG+LJE9quy2SQCe/u9REOL0KOp 0LqTUEJcLLB/9ysrq0QJNuR9W2petZ5VGc5ZW51xM9Ay7mNXTr4y4y7ax5fCM+xQUaVr y4/5/arTaL76MAtJb9IvOVwTXdSkRA8Q14zUKUho30UnTpCbxRYPIRMD10wDAYt9RCJI AhEbiEwaCp6onJWwTiBalqLh1/WT56EWzZaPeYBQaEIn0uA+EJUgcqp62dug2RGUlIjl eRB4D+oTVuZlXZesP8iyZF3XV32m7uCB11Mag5e5ZAmWB5Rh/YAdm34BfrwY4b3Qzxjz zHkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727687517; x=1728292317; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q7rvccsh9aj83xuH88lWH8I7b7DG49roHC3cpFazkmA=; b=phwu1sXgGt8O4jBurTA//PtJp8LaWlrOELDI8i4w2Q6+Wjv1ISMdnwG9+PDOms9+OF ginrbGsak/1+2V6S0UIEu5FBzunAFSlJTvHwf5miANRfg4iZAydu+bSdLw7OWLnBf76q RaEfaD3ZKc9Blk3VrFV5HQ3wiG1m8BLIsf0SSeZdzMmkVhyjvwL6djGlvj5HPwgUgmhU aw8AQSfa0npgECy0AvQknnLbDVrhCGKkweqWT4chL6XrkaFsVgKqGYSnv5HM+gCnFKuV MGGVd5AOWWG0SixuHzDxdI5nsCR3/y15iT5HXBX/Vw4Q4txl3wrMUErkaPM+ghl1FSse lzHA== X-Gm-Message-State: AOJu0YyVvb78wQRYYbDpyBkz3gzZ+H0aRQCz348iAquJwvA9UlwUMakQ uL9/zfhB1dd+5/lObf/1k4Q0wuGPZybY+z7Y3DKzdNKPdo5pS3DVZ4ESJ0DBnK5ijjhVFBViaRX W X-Google-Smtp-Source: AGHT+IFstc3+1ne36WuP/YJCvf2jT9N99VSaL7A6bUcIJt9pj3Tc4zUZ0TOsEst7di6EqbO2uglEeA== X-Received: by 2002:a5d:470f:0:b0:37c:cdb2:c4a4 with SMTP id ffacd0b85a97d-37cd5a831f1mr5001857f8f.7.1727687517039; Mon, 30 Sep 2024 02:11:57 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson Subject: [PATCH 07/12] target/mips: Replace MO_TE by mo_endian() Date: Mon, 30 Sep 2024 11:10:56 +0200 Message-ID: <20240930091101.40591-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930091101.40591-1-philmd@linaro.org> References: <20240930091101.40591-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727687635211116600 Replace compile-time MO_TE evaluation by runtime mo_endian() one, which expand target endianness from DisasContext. Mechanical change using: $ sed -i -e 's/MO_TE/mo_endian(ctx)/' \ $(git grep -l MO_TE target/mips) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/tcg/msa_helper.c | 2 +- target/mips/tcg/mxu_translate.c | 18 ++-- target/mips/tcg/translate.c | 120 +++++++++++----------- target/mips/tcg/tx79_translate.c | 8 +- target/mips/tcg/micromips_translate.c.inc | 22 ++-- target/mips/tcg/mips16e_translate.c.inc | 12 +-- target/mips/tcg/nanomips_translate.c.inc | 32 +++--- 7 files changed, 107 insertions(+), 107 deletions(-) diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index d2181763e7..0d517b8062 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8213,7 +8213,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_= t df, uint32_t wd, =20 #if !defined(CONFIG_USER_ONLY) #define MEMOP_IDX(DF) \ - MemOpIdx oi =3D make_memop_idx(MO_TE | DF | MO_UNALN, \ + MemOpIdx oi =3D make_memop_idx(mo_endian(dc) | DF | MO_UNALN, = \ mips_env_mmu_index(env)); #else #define MEMOP_IDX(DF) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translat= e.c index b221f7a4a0..f25fb8eda8 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -1533,7 +1533,7 @@ static void gen_mxu_s32ldxx(DisasContext *ctx, bool r= eversed, bool postinc) tcg_gen_add_tl(t0, t0, t1); =20 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, - (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) | + ((mo_endian(ctx) | MO_SL) ^ (reversed ? MO_BSWAP : = 0)) | ctx->default_tcg_memop_mask); gen_store_mxu_gpr(t1, XRa); =20 @@ -1569,7 +1569,7 @@ static void gen_mxu_s32stxx(DisasContext *ctx, bool r= eversed, bool postinc) =20 gen_load_mxu_gpr(t1, XRa); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) | + ((mo_endian(ctx) | MO_SL) ^ (reversed ? MO_BSWAP : = 0)) | ctx->default_tcg_memop_mask); =20 if (postinc) { @@ -1605,7 +1605,7 @@ static void gen_mxu_s32ldxvx(DisasContext *ctx, bool = reversed, tcg_gen_add_tl(t0, t0, t1); =20 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, - (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) | + ((mo_endian(ctx) | MO_SL) ^ (reversed ? MO_BSWAP : = 0)) | ctx->default_tcg_memop_mask); gen_store_mxu_gpr(t1, XRa); =20 @@ -1675,7 +1675,7 @@ static void gen_mxu_s32stxvx(DisasContext *ctx, bool = reversed, =20 gen_load_mxu_gpr(t1, XRa); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) | + ((mo_endian(ctx) | MO_SL) ^ (reversed ? MO_BSWAP : = 0)) | ctx->default_tcg_memop_mask); =20 if (postinc) { @@ -4803,19 +4803,19 @@ static void decode_opc_mxu__pool17(DisasContext *ct= x) =20 switch (opcode) { case OPC_MXU_LXW: - gen_mxu_lxx(ctx, strd2, MO_TE | MO_UL); + gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_UL); break; case OPC_MXU_LXB: - gen_mxu_lxx(ctx, strd2, MO_TE | MO_SB); + gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_SB); break; case OPC_MXU_LXH: - gen_mxu_lxx(ctx, strd2, MO_TE | MO_SW); + gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_SW); break; case OPC_MXU_LXBU: - gen_mxu_lxx(ctx, strd2, MO_TE | MO_UB); + gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_UB); break; case OPC_MXU_LXHU: - gen_mxu_lxx(ctx, strd2, MO_TE | MO_UW); + gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_UW); break; default: MIPS_INVAL("decode_opc_mxu"); diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 906fd3d73c..f2f974bfcd 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1964,9 +1964,9 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, = int mem_idx, \ gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); = \ } #endif -OP_LD_ATOMIC(ll, MO_TE | MO_SL); +OP_LD_ATOMIC(ll, mo_endian(dc) | MO_SL); #if defined(TARGET_MIPS64) -OP_LD_ATOMIC(lld, MO_TE | MO_UQ); +OP_LD_ATOMIC(lld, mo_endian(dc) | MO_UQ); #endif #undef OP_LD_ATOMIC =20 @@ -2073,12 +2073,12 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, switch (opc) { #if defined(TARGET_MIPS64) case OPC_LWU: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; case OPC_LD: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2090,33 +2090,33 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, case OPC_LDL: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UQ); + gen_lxl(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UQ); gen_store_gpr(t1, rt); break; case OPC_LDR: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UQ); + gen_lxr(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UQ); gen_store_gpr(t1, rt); break; case OPC_LDPC: t1 =3D tcg_constant_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UQ); gen_store_gpr(t0, rt); break; #endif case OPC_LWPC: t1 =3D tcg_constant_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL); + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SL); gen_store_gpr(t0, rt); break; case OPC_LWE: mem_idx =3D MIPS_HFLAG_UM; /* fall through */ case OPC_LW: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2124,7 +2124,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, mem_idx =3D MIPS_HFLAG_UM; /* fall through */ case OPC_LH: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SW | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2132,7 +2132,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, mem_idx =3D MIPS_HFLAG_UM; /* fall through */ case OPC_LHU: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UW | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2156,7 +2156,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, case OPC_LWL: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UL); + gen_lxl(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UL); tcg_gen_ext32s_tl(t1, t1); gen_store_gpr(t1, rt); break; @@ -2166,7 +2166,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, case OPC_LWR: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UL); + gen_lxr(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UL); tcg_gen_ext32s_tl(t1, t1); gen_store_gpr(t1, rt); break; @@ -2194,7 +2194,7 @@ static void gen_st(DisasContext *ctx, uint32_t opc, i= nt rt, switch (opc) { #if defined(TARGET_MIPS64) case OPC_SD: - tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); break; case OPC_SDL: @@ -2208,14 +2208,14 @@ static void gen_st(DisasContext *ctx, uint32_t opc,= int rt, mem_idx =3D MIPS_HFLAG_UM; /* fall through */ case OPC_SW: - tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); break; case OPC_SHE: mem_idx =3D MIPS_HFLAG_UM; /* fall through */ case OPC_SH: - tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UW | + tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UW | ctx->default_tcg_memop_mask); break; case OPC_SBE: @@ -2281,7 +2281,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t = opc, int ft, case OPC_LWC1: { TCGv_i32 fp0 =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL | + tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO= _SL | ctx->default_tcg_memop_mask); gen_store_fpr32(ctx, fp0, ft); } @@ -2290,14 +2290,14 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_= t opc, int ft, { TCGv_i32 fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, ft); - tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO= _UL | ctx->default_tcg_memop_mask); } break; case OPC_LDC1: { TCGv_i64 fp0 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO= _UQ | ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, fp0, ft); } @@ -2306,7 +2306,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t = opc, int ft, { TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, ft); - tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO= _UQ | ctx->default_tcg_memop_mask); } break; @@ -2987,14 +2987,14 @@ static inline void gen_pcrel(DisasContext *ctx, int= opc, target_ulong pc, case R6_OPC_LWPC: offset =3D sextract32(ctx->opcode << 2, 0, 21); addr =3D addr_add(ctx, pc, offset); - gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_SL); + gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_SL); break; #if defined(TARGET_MIPS64) case OPC_LWUPC: check_mips_64(ctx); offset =3D sextract32(ctx->opcode << 2, 0, 21); addr =3D addr_add(ctx, pc, offset); - gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UL); + gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UL); break; #endif default: @@ -3021,7 +3021,7 @@ static inline void gen_pcrel(DisasContext *ctx, int o= pc, target_ulong pc, check_mips_64(ctx); offset =3D sextract32(ctx->opcode << 3, 0, 21); addr =3D addr_add(ctx, (pc & ~0x7), offset); - gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UQ); + gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UQ); break; #endif default: @@ -4160,10 +4160,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, i= nt rt, case OPC_GSLQ: t1 =3D tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rt); gen_store_gpr(t0, lsq_rt1); @@ -4172,10 +4172,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, i= nt rt, check_cp1_enabled(ctx); t1 =3D tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, t1, rt); gen_store_fpr64(ctx, t0, lsq_rt1); @@ -4184,11 +4184,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, i= nt rt, t1 =3D tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); gen_load_gpr(t1, lsq_rt1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); break; case OPC_GSSQC1: @@ -4196,11 +4196,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, i= nt rt, t1 =3D tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); gen_load_fpr64(ctx, t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); gen_load_fpr64(ctx, t1, lsq_rt1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); break; #endif @@ -4213,7 +4213,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_load_fpr32(ctx, fp0, rt); t1 =3D tcg_temp_new(); tcg_gen_ext_i32_tl(t1, fp0); - gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL); + gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); tcg_gen_trunc_tl_i32(fp0, t1); gen_store_fpr32(ctx, fp0, rt); break; @@ -4224,7 +4224,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_load_fpr32(ctx, fp0, rt); t1 =3D tcg_temp_new(); tcg_gen_ext_i32_tl(t1, fp0); - gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL); + gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); tcg_gen_trunc_tl_i32(fp0, t1); gen_store_fpr32(ctx, fp0, rt); break; @@ -4234,7 +4234,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_base_offset_addr(ctx, t0, rs, shf_offset); t1 =3D tcg_temp_new(); gen_load_fpr64(ctx, t1, rt); - gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ); + gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); gen_store_fpr64(ctx, t1, rt); break; case OPC_GSLDRC1: @@ -4242,7 +4242,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_base_offset_addr(ctx, t0, rs, shf_offset); t1 =3D tcg_temp_new(); gen_load_fpr64(ctx, t1, rt); - gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ); + gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); gen_store_fpr64(ctx, t1, rt); break; #endif @@ -4360,7 +4360,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, gen_store_gpr(t0, rt); break; case OPC_GSLHX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -4369,7 +4369,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, if (rd) { gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -4379,7 +4379,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, if (rd) { gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -4390,7 +4390,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } fp0 =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL | + tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); gen_store_fpr32(ctx, fp0, rt); break; @@ -4400,7 +4400,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, if (rd) { gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, t0, rt); break; @@ -4413,34 +4413,34 @@ static void gen_loongson_lsdc2(DisasContext *ctx, i= nt rt, case OPC_GSSHX: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UW | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UW | ctx->default_tcg_memop_mask); break; case OPC_GSSWX: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); break; #if defined(TARGET_MIPS64) case OPC_GSSDX: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); break; #endif case OPC_GSSWXC1: fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, rt); - tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); break; #if defined(TARGET_MIPS64) case OPC_GSSDXC1: t1 =3D tcg_temp_new(); gen_load_fpr64(ctx, t1, rt); - tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); break; #endif @@ -10779,7 +10779,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, { TCGv_i32 fp0 =3D tcg_temp_new_i32(); =20 - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_S= L); tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32(ctx, fp0, fd); } @@ -10789,7 +10789,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, check_cp1_registers(ctx, fd); { TCGv_i64 fp0 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO= _UQ); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10799,7 +10799,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, { TCGv_i64 fp0 =3D tcg_temp_new_i64(); =20 - tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO= _UQ); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10808,7 +10808,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, { TCGv_i32 fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); - tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL); + tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO= _UL); } break; case OPC_SDXC1: @@ -10817,7 +10817,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, { TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO= _UQ); } break; case OPC_SUXC1: @@ -10826,7 +10826,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, { TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO= _UQ); } break; } @@ -11476,7 +11476,7 @@ void gen_ldxs(DisasContext *ctx, int base, int inde= x, int rd) gen_op_addr_add(ctx, t0, t1, t0); } =20 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); gen_store_gpr(t1, rd); } =20 @@ -11567,16 +11567,16 @@ static void gen_mips_lx(DisasContext *ctx, uint32= _t opc, gen_store_gpr(t0, rd); break; case OPC_LHX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW); gen_store_gpr(t0, rd); break; case OPC_LWX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); gen_store_gpr(t0, rd); break; #if defined(TARGET_MIPS64) case OPC_LDX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); gen_store_gpr(t0, rd); break; #endif @@ -13719,7 +13719,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) } break; case R6_OPC_SC: - gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false); + gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, false); break; case R6_OPC_LL: gen_ld(ctx, op1, rt, rs, imm); @@ -13765,7 +13765,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) #endif #if defined(TARGET_MIPS64) case R6_OPC_SCD: - gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false); + gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_UQ, false); break; case R6_OPC_LLD: gen_ld(ctx, op1, rt, rs, imm); @@ -14448,7 +14448,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) return; case OPC_SCE: check_cp0_enabled(ctx); - gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, true); + gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, true); return; case OPC_CACHEE: check_eva(ctx); @@ -14912,7 +14912,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); } - gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false); + gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, false); break; case OPC_CACHE: check_cp0_enabled(ctx); @@ -15191,7 +15191,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) check_insn_opc_user_only(ctx, INSN_R5900); } check_mips_64(ctx); - gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false); + gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_UQ, false); break; case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */ if (ctx->insn_flags & ISA_MIPS_R6) { diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_transl= ate.c index 1d290b86a9..ae3f5e19c4 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -340,12 +340,12 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a) tcg_gen_andi_tl(addr, addr, ~0xf); =20 /* Lower half */ - tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ); gen_store_gpr(t0, a->rt); =20 /* Upper half */ tcg_gen_addi_i64(addr, addr, 8); - tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ); gen_store_gpr_hi(t0, a->rt); return true; } @@ -364,12 +364,12 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a) =20 /* Lower half */ gen_load_gpr(t0, a->rt); - tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ); =20 /* Upper half */ tcg_gen_addi_i64(addr, addr, 8); gen_load_gpr_hi(t0, a->rt); - tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ); return true; } =20 diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/mi= cromips_translate.c.inc index 343d64a0e8..171508f7de 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -977,23 +977,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t= opc, int rd, gen_reserved_instruction(ctx); return; } - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 4); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd + 1); break; case SWP: gen_load_gpr(t1, rd); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); tcg_gen_movi_tl(t1, 4); gen_op_addr_add(ctx, t0, t0, t1); gen_load_gpr(t1, rd + 1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); break; #ifdef TARGET_MIPS64 @@ -1002,23 +1002,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32= _t opc, int rd, gen_reserved_instruction(ctx); return; } - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 8); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd + 1); break; case SDP: gen_load_gpr(t1, rd); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); tcg_gen_movi_tl(t1, 8); gen_op_addr_add(ctx, t0, t0, t1); gen_load_gpr(t1, rd + 1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); break; #endif @@ -2572,13 +2572,13 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_st(ctx, mips32_op, rt, rs, offset); break; case SC: - gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, false); + gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_SL, false= ); break; #if defined(TARGET_MIPS64) case SCD: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_UQ, false); + gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_UQ, false= ); break; #endif case LD_EVA: @@ -2659,7 +2659,7 @@ static void decode_micromips32_opc(CPUMIPSState *env,= DisasContext *ctx) mips32_op =3D OPC_SHE; goto do_st_lr; case SCE: - gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, true); + gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_SL, t= rue); break; case SWE: mips32_op =3D OPC_SWE; diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips= 16e_translate.c.inc index 9dd867fe89..3943bf3368 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -135,7 +135,7 @@ static void decr_and_store(DisasContext *ctx, unsigned = regidx, TCGv t0) tcg_gen_movi_tl(t2, -4); gen_op_addr_add(ctx, t0, t0, t2); gen_load_gpr(t1, regidx); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); } =20 @@ -184,25 +184,25 @@ static void gen_mips16_save(DisasContext *ctx, case 4: gen_base_offset_addr(ctx, t0, 29, 12); gen_load_gpr(t1, 7); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); /* Fall through */ case 3: gen_base_offset_addr(ctx, t0, 29, 8); gen_load_gpr(t1, 6); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); /* Fall through */ case 2: gen_base_offset_addr(ctx, t0, 29, 4); gen_load_gpr(t1, 5); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); /* Fall through */ case 1: gen_base_offset_addr(ctx, t0, 29, 0); gen_load_gpr(t1, 4); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); } =20 @@ -297,7 +297,7 @@ static void decr_and_load(DisasContext *ctx, unsigned r= egidx, TCGv t0) =20 tcg_gen_movi_tl(t2, -4); gen_op_addr_add(ctx, t0, t0, t2); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t1, regidx); } diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nan= omips_translate.c.inc index 40ef0346a7..65e6e759e4 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -998,7 +998,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, = int16_t offset, TCGv tmp2 =3D tcg_temp_new(); =20 gen_base_offset_addr(ctx, taddr, base, offset); - tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TE | MO_UQ | MO_ALIG= N); + tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, mo_endian(ctx) | MO_UQ = | MO_ALIGN); if (cpu_is_bigendian(ctx)) { tcg_gen_extr_i64_tl(tmp2, tmp1, tval); } else { @@ -1075,7 +1075,7 @@ static void gen_save(DisasContext *ctx, uint8_t rt, u= int8_t count, gen_base_offset_addr(ctx, va, 29, this_offset); gen_load_gpr(t0, this_rt); tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx, - (MO_TE | MO_UL | ctx->default_tcg_memop_mask)); + (mo_endian(ctx) | MO_UL | ctx->default_tcg_memo= p_mask)); counter++; } =20 @@ -1095,7 +1095,7 @@ static void gen_restore(DisasContext *ctx, uint8_t rt= , uint8_t count, int this_rt =3D use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f= ); int this_offset =3D u - ((counter + 1) << 2); gen_base_offset_addr(ctx, va, 29, this_offset); - tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TE | MO_SL | + tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); tcg_gen_ext32s_tl(t0, t0); gen_store_gpr(t0, this_rt); @@ -2647,13 +2647,13 @@ static void gen_p_lsx(DisasContext *ctx, int rd, in= t rs, int rt) case NM_LHX: /*case NM_LHXS:*/ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TE | MO_SW | ctx->default_tcg_memop_mask); + mo_endian(ctx) | MO_SW | ctx->default_tcg_memop= _mask); gen_store_gpr(t0, rd); break; case NM_LWX: /*case NM_LWXS:*/ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TE | MO_SL | ctx->default_tcg_memop_mask); + mo_endian(ctx) | MO_SL | ctx->default_tcg_memop= _mask); gen_store_gpr(t0, rd); break; case NM_LBUX: @@ -2663,7 +2663,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int = rs, int rt) case NM_LHUX: /*case NM_LHUXS:*/ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TE | MO_UW | ctx->default_tcg_memop_mask); + mo_endian(ctx) | MO_UW | ctx->default_tcg_memop= _mask); gen_store_gpr(t0, rd); break; case NM_SBX: @@ -2676,14 +2676,14 @@ static void gen_p_lsx(DisasContext *ctx, int rd, in= t rs, int rt) check_nms(ctx); gen_load_gpr(t1, rd); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_TE | MO_UW | ctx->default_tcg_memop_mask); + mo_endian(ctx) | MO_UW | ctx->default_tcg_memop= _mask); break; case NM_SWX: /*case NM_SWXS:*/ check_nms(ctx); gen_load_gpr(t1, rd); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_TE | MO_UL | ctx->default_tcg_memop_mask); + mo_endian(ctx) | MO_UL | ctx->default_tcg_memop= _mask); break; case NM_LWC1X: /*case NM_LWC1XS:*/ @@ -3737,7 +3737,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) =20 tcg_gen_movi_tl(t0, addr); tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, - MO_TE | MO_SL | ctx->default_tcg_me= mop_mask); + mo_endian(ctx) | MO_SL | ctx->defau= lt_tcg_memop_mask); } break; case NM_SWPC48: @@ -3754,7 +3754,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_load_gpr(t1, rt); =20 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_TE | MO_UL | ctx->default_tcg_me= mop_mask); + mo_endian(ctx) | MO_UL | ctx->defau= lt_tcg_memop_mask); } break; default: @@ -4132,13 +4132,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) =20 switch (extract32(ctx->opcode, 11, 4)) { case NM_UALH: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE= | MO_SW | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_en= dian(ctx) | MO_SW | MO_UNALN); gen_store_gpr(t0, rt); break; case NM_UASH: gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE= | MO_UW | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_en= dian(ctx) | MO_UW | MO_UNALN); break; } @@ -4161,7 +4161,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) case NM_P_SC: switch (ctx->opcode & 0x03) { case NM_SC: - gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, false); + gen_st_cond(ctx, rt, rs, s, mo_endian(ctx) | MO_SL= , false); break; case NM_SCWP: check_xnp(ctx); @@ -4274,7 +4274,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) check_xnp(ctx); check_eva(ctx); check_cp0_enabled(ctx); - gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, true); + gen_st_cond(ctx, rt, rs, s, mo_endian(ctx) | MO_SL= , true); break; case NM_SCWPE: check_xnp(ctx); @@ -4317,7 +4317,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) switch (extract32(ctx->opcode, 11, 1)) { case NM_LWM: tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx, - memop | MO_TE | MO_SL); + memop | mo_endian(ctx) | MO= _SL); gen_store_gpr(t1, this_rt); if ((this_rt =3D=3D rs) && (counter !=3D (count - 1))) { @@ -4328,7 +4328,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) this_rt =3D (rt =3D=3D 0) ? 0 : this_rt; gen_load_gpr(t1, this_rt); tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx, - memop | MO_TE | MO_UL); + memop | mo_endian(ctx) | MO= _UL); break; } counter++; --=20 2.45.2 From nobody Sat Dec 21 15:47:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727687602; cv=none; d=zohomail.com; s=zohoarc; b=EMmiBV+JhvGkPmVRgt4YJqSZ/3/n6WlajYtDoGUhpC8Kc2Lg1ITZbK7LoeoyCUssBbMS9HLPXqEbPAILHK2J5NzXwf3UwR/GoukqTOfrwCdHw+ra6TUlnfADQD+W7ePn89MUYhzQD60uNQfPYS+EPSgEGtOVNmAR0/qvcamEfco= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727687602; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=yZ3s4BKBUIpf605yoFIcvuj2HOu5NdByFuIUuDf7Wlk=; b=WJ3zp5jeSdD857mxcC4oFd1o/V5O7JFyNMITMzc9hJ7d0Z6Th7t5Z3hhNpXzD8hi924dALfbzH67ax3dPN4YS6dONh9wkEJCaasJ3QZ6vzACU9VNvLpHEwjSzSIe6umhHlySo8b90IcF3PPdv2nsdpWzWtdIMyfF8WEt0ACIENc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727687602227787.2205818251547; Mon, 30 Sep 2024 02:13:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svCS8-0002oD-4u; Mon, 30 Sep 2024 05:12:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svCRs-0002Kc-Ri for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:12:10 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svCRr-0004dn-1y for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:12:08 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-42cae4eb026so39745145e9.0 for ; Mon, 30 Sep 2024 02:12:06 -0700 (PDT) Received: from localhost.localdomain (183.red-88-28-18.dynamicip.rima-tde.net. [88.28.18.183]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e96a362bcsm144722025e9.36.2024.09.30.02.12.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 02:12:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727687525; x=1728292325; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yZ3s4BKBUIpf605yoFIcvuj2HOu5NdByFuIUuDf7Wlk=; b=kbNjyS7Art1bzFQ8q78iPqr0pPFkUBNtsOocIeDfsZhl7jRVgwfvTIHhHOJOEmH+Rk ilMrRyuN7oKVzRNapoi0iqsTGt99OpRfnJyc0UEVDHihuUvZx6v/h5LSbCKdiqnc6YaJ lPQ3dHn/i3utVcdGmKOBBYLoFiHS0SyZb2tvsshcyk3jDa+zhwslZGhx4QsBOOmsijYM 8O1G75zjHGGPA8a0l/0Fe+0KHz0lx9zFK0OzJ83//PF27J/a8rP75KManXJaKDgitF2C hv/oOQyZemE/oWIXxBoZyq/7ad+PWsG4I10ZXIrx1qaeDprend74sR30vQxLdbgOiD66 mz4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727687525; x=1728292325; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yZ3s4BKBUIpf605yoFIcvuj2HOu5NdByFuIUuDf7Wlk=; b=Q6UxFvAmgx4T3tYqZsl/Gks4ua/RyqmYOPDu+3Ieskdidu8bXpUAGyPYTP9VS/3ORb aWcOi9KciFmcKk4YCozqcua/hkplyk2/PvFMUl3dEId2nepPa6v/m4VgsNLc7epJKtvF PmmQ6K0LgI16rz+ZnxqCZoBgRcagl3xZUDcJVtq5nbYNDBQnbmUzN7HnDRgubYkiuq6Z t+pV2XmovRXnWoa0SWofmSwSnU6hziy+ZRqZ9NFfK8jtyEHrNBiQBITh9qITOu9ZUP7K Nnt4h7uDTpw+y9gP2wQTPHDpBfUUc3bT+QeGODk0xVu+oqgy83rog63xPRrleEn2W16G 9g1A== X-Gm-Message-State: AOJu0Yyf2WApoiH4qDUvu3ByTIVY+BYLZjpDNU/ghtnt+D9emkAM/FvD Kooqac3ycet/V0Ycp4XuVth7ZRx/o6f5QPGT6egPIkaR7KXSOy4XdqgzBs2HrAwjtYJKpr/Tz9n e X-Google-Smtp-Source: AGHT+IESSYBEffHZ9mn3SZL6r9LRgoZ2v0CCuUL5iPDughSA3ypcTq5hwUBQVEPDZiam+pOV48FEXA== X-Received: by 2002:a05:600c:1ca2:b0:428:f0c2:ef4a with SMTP id 5b1f17b1804b1-42f58433166mr75603565e9.13.1727687525081; Mon, 30 Sep 2024 02:12:05 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson Subject: [PATCH 08/12] target/mips: Expose MIPSCPU::is_big_endian property Date: Mon, 30 Sep 2024 11:10:57 +0200 Message-ID: <20240930091101.40591-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930091101.40591-1-philmd@linaro.org> References: <20240930091101.40591-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727687602892116600 Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/cpu.h | 3 +++ target/mips/cpu.c | 9 ++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3e906a175a..070e11fe0d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1209,6 +1209,9 @@ struct ArchCPU { =20 Clock *clock; Clock *count_div; /* Divider for CP0_Count clock */ + + /* Properties */ + bool is_big_endian; }; =20 /** diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 89655b1900..982f5bb4e2 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -200,7 +200,8 @@ static void mips_cpu_reset_hold(Object *obj, ResetType = type) =20 /* Reset registers to their default values */ env->CP0_PRid =3D env->cpu_model->CP0_PRid; - env->CP0_Config0 =3D env->cpu_model->CP0_Config0; + env->CP0_Config0 =3D deposit32(env->cpu_model->CP0_Config0, + CP0C0_BE, 1, cpu->is_big_endian); #if TARGET_BIG_ENDIAN env->CP0_Config0 |=3D (1 << CP0C0_BE); #endif @@ -541,6 +542,11 @@ static const struct SysemuCPUOps mips_sysemu_ops =3D { }; #endif =20 +static Property mips_cpu_properties[] =3D { + DEFINE_PROP_BOOL("big-endian", MIPSCPU, is_big_endian, TARGET_BIG_ENDI= AN), + DEFINE_PROP_END_OF_LIST(), +}; + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" /* @@ -571,6 +577,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) DeviceClass *dc =3D DEVICE_CLASS(c); ResettableClass *rc =3D RESETTABLE_CLASS(c); =20 + device_class_set_props(dc, mips_cpu_properties); device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL, --=20 2.45.2 From nobody Sat Dec 21 15:47:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727687621; cv=none; d=zohomail.com; s=zohoarc; b=f7BskKJy1sX0Mu1jK5fTbWRYEIjKZAlSHo0y6whH6o2EcGS3Yv9skB3vOxSNUCfWrUxKHAspaHm9sH2Xt4pq21NbngBKhBLSdzdmaBne4jFacJRQu+45vcNGOVLNHn7lqETOKBL4lp4azWdzOV9bAZOBN2p/zhC3ooblbZbZYSQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727687621; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=uCiZY+YuwU08zy4bXykcCZ7CJfeAV953m1oo4BHo/5c=; b=PrDe0Pla49OCfUaoaFilVj56pmEfgvZoQ3bJk9iekPuJYQ4hm5Q2mKAXknolkcv1SB7/zpOTVdgjrDQ9QF6eBxgof3ygZAKMY6p66xrG+vDEGlMcyNQswSe3eY+d3AxJ8EdXoqx/AiOhBLL4u+I590pc3HFhKHl7i7N1JSmzGCw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727687621568347.36001012789063; Mon, 30 Sep 2024 02:13:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svCSG-0003lb-6n; Mon, 30 Sep 2024 05:12:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svCS0-0002tA-9A for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:12:21 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svCRy-0004eO-LY for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:12:16 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-42e7b7bef42so32923935e9.3 for ; Mon, 30 Sep 2024 02:12:14 -0700 (PDT) Received: from localhost.localdomain (183.red-88-28-18.dynamicip.rima-tde.net. [88.28.18.183]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e969ddcc4sm144070915e9.10.2024.09.30.02.12.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 02:12:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727687532; x=1728292332; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uCiZY+YuwU08zy4bXykcCZ7CJfeAV953m1oo4BHo/5c=; b=w9cmntIjhopWQZQqtwSRnzBzsoK0qJgqvXmJAoLXJMKw9UQwoUW2xfYgyuQxhG24IR zyYyi08CgxPmRodDzx2xX+ilDomS/tiJR9/NGystWpfylG4ak+gci3LtkqUFOFsc2mRw fz6L8BWiRWVNnbu0THmHxkwGbhoQBADy7is7pNu9jv1nguxEgG5HojruuTZLx9gwWas9 ogvrYM5yAWbX425MsSW+9LbDLCdXm7v4KTiEadnF008sOFPR9X+sPWOB2weXF6Zn5/V3 SAnRSvKngVaauBWWJekS1XkX/pvsuPAPhMrKLb5b8P8vl/NwjweXwMBaF8T0iOs19A63 cHNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727687532; x=1728292332; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uCiZY+YuwU08zy4bXykcCZ7CJfeAV953m1oo4BHo/5c=; b=XAZCHQqRHStva04Z8NfybyJG523yqFVTUJNDKkNzKFYpRP7BElCCSInaDi4LLUKPNU XRr46ct+VaL1CgSHOqIA34xeJotyWyI9FsF5GiLoYMd1WNa8Wc+siNLMrA+97ns+/d0/ udCbZrgrOqvvBTkYX9bHmSAhaZ7yVihLD/9gyNmlXEo7N88Ik0FBoXNEZNtJuUy3OcrU UchwUcw7ww/eZpf3B9I/vqyA/gxjZO5C0UfMZVUyJF/ivWPdHXOIfRxdaXZW4lGKBgjz ObyaphYPqSls1ZIH6UXOSsmXtxLMMq78/oa5wINM0Qg1OVYF6xt1Fmyy1XWPD0Xsbd0L 7JXg== X-Gm-Message-State: AOJu0YyV9hcgA2moImXF8u6oXAr+Udz7MdiyJhRSpZxucMMVnwXAH39Y 6UnKvpSlqO3T8BgG4kbl3m5Tm1R4AdtBBQt3ETt1BTm3zl5JIomhUFoRMFHbylutHBWx0lCJFqn o X-Google-Smtp-Source: AGHT+IEpC7xT+I+0JsJnymmQxAWzUFTkEtZ3ucW8tIEyTP63uiOEz9MGVs19/RBtsAgR+MmdmhJYeA== X-Received: by 2002:a05:600c:1ca1:b0:42a:a6aa:4135 with SMTP id 5b1f17b1804b1-42f5844cbd7mr77550695e9.20.1727687532163; Mon, 30 Sep 2024 02:12:12 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson Subject: [PATCH 09/12] hw/mips/cps: Set the vCPU 'cpu-big-endian' property Date: Mon, 30 Sep 2024 11:10:58 +0200 Message-ID: <20240930091101.40591-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930091101.40591-1-philmd@linaro.org> References: <20240930091101.40591-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727687623016116600 Have the CPS expose a 'cpu-big-endian' property so it can set it to the vCPUs it creates. Note, since the number of vCPUs created is dynamic, we can not use QOM aliases. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- include/hw/mips/cps.h | 1 + hw/mips/cps.c | 4 ++++ hw/mips/malta.c | 2 ++ 3 files changed, 7 insertions(+) diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index 04d636246a..05ef9f76b7 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -38,6 +38,7 @@ struct MIPSCPSState { uint32_t num_vp; uint32_t num_irq; char *cpu_type; + bool cpu_is_bigendian; =20 MemoryRegion container; MIPSGCRState gcr; diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 07b73b0a1f..13046628cd 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -77,6 +77,9 @@ static void mips_cps_realize(DeviceState *dev, Error **er= rp) MIPSCPU *cpu =3D MIPS_CPU(object_new(s->cpu_type)); CPUMIPSState *env =3D &cpu->env; =20 + object_property_set_bool(OBJECT(cpu), "big-endian", s->cpu_is_bige= ndian, + &error_abort); + /* All VPs are halted on reset. Leave powering up to CPC. */ object_property_set_bool(OBJECT(cpu), "start-powered-off", true, &error_abort); @@ -167,6 +170,7 @@ static Property mips_cps_properties[] =3D { DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1), DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256), DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type), + DEFINE_PROP_BOOL("cpu-big-endian", MIPSCPSState, cpu_is_bigendian, fal= se), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 6e73c896ff..a0757f251a 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1055,6 +1055,8 @@ static void create_cps(MachineState *ms, MaltaState *= s, object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, &error_fatal); + object_property_set_bool(OBJECT(&s->cps), "cpu-big-endian", + TARGET_BIG_ENDIAN, &error_abort); object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus, &error_fatal); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); --=20 2.45.2 From nobody Sat Dec 21 15:47:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727687634; cv=none; d=zohomail.com; s=zohoarc; b=GE/pAwGFDNxnEQvzlyPwC41OwMfUlbmy2l7aKlKhDzyEsCLY9QZXggd8+2WQs+risQOfVnIqye5E0frPhk1UqHvcW9l7XQvyQDkS8ks7zI8oI79om6FxSvu0+D7Bp07fDUfNAH2FoZkpcKq+0M7ztzES1NhSsKRLcqCpHtvbVfI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727687634; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=b77I1JPh4FFui3m8ARcyeS7xVA2tnhUm1eKsfIObl9M=; b=g7k3J/AAKgfyLAXQ2g9uMHyYAFmhING/fwSMnptPzjbJSzH2axJ0odyX+7nA+CCy7inPEl9OYqHkv3K4TyWE4HGSasJg/FmCE0f4Sfh1epaU5j6r4OlRWr6lHQ8Q+nlU8YCsAOzQh0HaIJWHERTonEvfb7fW5ilm4rzGD0kxgQ8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727687634757658.3919471193524; Mon, 30 Sep 2024 02:13:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svCSH-00047B-4r; Mon, 30 Sep 2024 05:12:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svCS7-0003NJ-5F for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:12:25 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svCS5-0004fk-D2 for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:12:22 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-42f6bec84b5so4486685e9.1 for ; Mon, 30 Sep 2024 02:12:20 -0700 (PDT) Received: from localhost.localdomain (183.red-88-28-18.dynamicip.rima-tde.net. [88.28.18.183]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd565de3asm8524894f8f.29.2024.09.30.02.12.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 02:12:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727687539; x=1728292339; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b77I1JPh4FFui3m8ARcyeS7xVA2tnhUm1eKsfIObl9M=; b=PdNt4p/RdUVDbUtNy0KaPTGMBnjdXXJuB8xM8vil4//+bNgExELSuC/Qw1b3UMwwvC Z8IqTQUfNp73c1jD6lGaUU29vTIClLijH0c9Zoz/O4iPzuK/tCjP4oEeZZicXyu/IyT1 wByZ+xCtxNSi5dQ4PKJ5Q3VonlgoGK562gyxRkhD38R7X10O3+yvGzHOcHC6OSoZJZfy y9Vjwgx4y1O7YzmTElyIgsqp0VEppqs9ovIXl6OIwDnDgEOss+7Hn+FER+M93jzZwAFN TYn6seKVSR/121tLHKJIOLmygbMxfuKKPEXqyD+HCyNpRjo2e6pRIEuOaxWwAKOLIxkp 7ljQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727687539; x=1728292339; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b77I1JPh4FFui3m8ARcyeS7xVA2tnhUm1eKsfIObl9M=; b=K0npIrWfUU01EroetKwb0TCwFECVIyzGwPoOp5A8Q42PSSKzD1GoQeNEUepOJCdNyQ 9FpIC62xWI8g1yEWgq3JY+rHvMo86T5zAZwklXvuQDCO9j/uaVh7ld+daduoBKERWrKa lUR+O+Z5Hq+i4Uq1gc2PQD39hgPRISTVVCiNRDSLUUU9nwFtecm4dSIzxuE/t40K5nLF hN+/VcUbyZHIZ7HW4lZ6nBdjFuGsXG5/n0PDF7TT0kiZ1oF3QOptsURLyLvZeYx6OqVA 6Csj1KpyLhfMWHbwST8PFqPFyfCQcjwatbklgWZjLpM6f4zZQ4yU6yuTsJP+sKrzxclD Bj+A== X-Gm-Message-State: AOJu0Yw3W33IIqsUUMkpe61qGmI813LVx+KoSeXRju9SscXtA/fu9Ie2 U84exW9j66+6LTv7kEFKmcXhuQYrGv4chmuWGo/tCEz3OQt9V7VVIUssYsuLAjcWVkvY7w/DzNX c X-Google-Smtp-Source: AGHT+IFwxcPXPCcwzJxfDAGB6L56t56fLXhjD9Oy/3J9Aq658n/SIKQz75HLX0iq+yh/L4uBikgyNg== X-Received: by 2002:a05:600c:3b8c:b0:42c:be90:fa1b with SMTP id 5b1f17b1804b1-42f584335f0mr86822345e9.14.1727687538838; Mon, 30 Sep 2024 02:12:18 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson Subject: [PATCH 10/12] hw/mips: Have mips_cpu_create_with_clock() take an endianness argument Date: Mon, 30 Sep 2024 11:10:59 +0200 Message-ID: <20240930091101.40591-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930091101.40591-1-philmd@linaro.org> References: <20240930091101.40591-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727687635082116600 mips_cpu_create_with_clock() creates a vCPU. Pass it the vCPU endianness requested by argument. Update the board call sites. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/cpu.h | 4 +++- hw/mips/fuloong2e.c | 2 +- hw/mips/jazz.c | 2 +- hw/mips/loongson3_virt.c | 2 +- hw/mips/malta.c | 3 ++- hw/mips/mipssim.c | 2 +- target/mips/cpu.c | 5 ++++- 7 files changed, 13 insertions(+), 7 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 070e11fe0d..a4a46ebbe9 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1376,12 +1376,14 @@ static inline void cpu_get_tb_cpu_state(CPUMIPSStat= e *env, vaddr *pc, * mips_cpu_create_with_clock: * @typename: a MIPS CPU type. * @cpu_refclk: this cpu input clock (an output clock of another device) + * @is_big_endian: whether this CPU is configured in big endianness * * Instantiates a MIPS CPU, set the input clock of the CPU to @cpu_refclk, * then realizes the CPU. * * Returns: A #CPUState or %NULL if an error occurred. */ -MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refcl= k); +MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refcl= k, + bool is_big_endian); =20 #endif /* MIPS_CPU_H */ diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 4fe5108845..50a3f06723 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -230,7 +230,7 @@ static void mips_fuloong2e_init(MachineState *machine) clock_set_hz(cpuclk, 533080000); /* ~533 MHz */ =20 /* init CPUs */ - cpu =3D mips_cpu_create_with_clock(machine->cpu_type, cpuclk); + cpu =3D mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false); env =3D &cpu->env; =20 qemu_register_reset(main_cpu_reset, cpu); diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 0d44e19707..812e8cbcab 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -212,7 +212,7 @@ static void mips_jazz_init(MachineState *machine, * ext_clk[jazz_model].pll_mult); =20 /* init CPUs */ - cpu =3D mips_cpu_create_with_clock(machine->cpu_type, cpuclk); + cpu =3D mips_cpu_create_with_clock(machine->cpu_type, cpuclk, TARGET_B= IG_ENDIAN); env =3D &cpu->env; qemu_register_reset(main_cpu_reset, cpu); =20 diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index 2067b4fecb..25fa94ee68 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -567,7 +567,7 @@ static void mips_loongson3_virt_init(MachineState *mach= ine) int ip; =20 /* init CPUs */ - cpu =3D mips_cpu_create_with_clock(machine->cpu_type, cpuclk); + cpu =3D mips_cpu_create_with_clock(machine->cpu_type, cpuclk, fals= e); =20 /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); diff --git a/hw/mips/malta.c b/hw/mips/malta.c index a0757f251a..71cc11fc45 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1035,7 +1035,8 @@ static void create_cpu_without_cps(MachineState *ms, = MaltaState *s, int i; =20 for (i =3D 0; i < ms->smp.cpus; i++) { - cpu =3D mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk); + cpu =3D mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk, + TARGET_BIG_ENDIAN); =20 /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index 9170d6c474..80b4a2c00d 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -160,7 +160,7 @@ mips_mipssim_init(MachineState *machine) #endif =20 /* Init CPUs. */ - cpu =3D mips_cpu_create_with_clock(machine->cpu_type, cpuclk); + cpu =3D mips_cpu_create_with_clock(machine->cpu_type, cpuclk, TARGET_B= IG_ENDIAN); env =3D &cpu->env; =20 reset_info =3D g_new0(ResetData, 1); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 982f5bb4e2..02e2e72f2d 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -646,12 +646,15 @@ static void mips_cpu_register_types(void) type_init(mips_cpu_register_types) =20 /* Could be used by generic CPU object */ -MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refcl= k) +MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refcl= k, + bool is_big_endian) { DeviceState *cpu; =20 cpu =3D DEVICE(object_new(cpu_type)); qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); + object_property_set_bool(OBJECT(cpu), "big-endian", is_big_endian, + &error_abort); qdev_realize(cpu, NULL, &error_abort); =20 return MIPS_CPU(cpu); --=20 2.45.2 From nobody Sat Dec 21 15:47:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727687562; cv=none; d=zohomail.com; s=zohoarc; b=EJKeB3El6hvcldNm1AE0tYgoPXsDxsmj5nI0AQZaNPs8ko5WHrq0kCyFoq3rqWR9BhINIAYxMDqw7d+qew243ZfEsvCuUqST7mTis4kXhyZHbc8DCHS5vx5ytuRKAndbuvvf+QB9/qaGYg32pboAzGXTGN6ixf2ttO+20HrHViw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727687562; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xp7nwUCJaW/bkSknjoRe7vWWzJDVDixFzfBIDbsBbN4=; b=Mo18lKAJNqBZe2xlRtek/92hi8RvAg9uI3ezsj8gQjmIWxiIGvyXxM/a916t7GVzfTSgr33QSVMwpuCmSyehL8NQIPAgh05YzHBULMO5qJxkde7Yxh4Sui+3ZNaPjjFD0DlvToi66Zhoj+w1Hkxrl11mNAiiVHbBWEVVTc9f8LY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17276875624801002.1676712655352; Mon, 30 Sep 2024 02:12:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svCSJ-0004Xl-Gy; Mon, 30 Sep 2024 05:12:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svCSD-0003pg-8B for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:12:31 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svCSB-0004gP-Fe for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:12:28 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-37cc810ce73so2354718f8f.1 for ; Mon, 30 Sep 2024 02:12:27 -0700 (PDT) Received: from localhost.localdomain (183.red-88-28-18.dynamicip.rima-tde.net. [88.28.18.183]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd574282esm8469346f8f.104.2024.09.30.02.12.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 02:12:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727687545; x=1728292345; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xp7nwUCJaW/bkSknjoRe7vWWzJDVDixFzfBIDbsBbN4=; b=GGPZEOA8hogiznbFQswVoWayJ0t63tZGAlYPlzg2/GXS592aabz/XDD0I81nvVnkQl SenxeqWuE9pr0ZNGThrzk4jhD6ey98SiWHjkL+/Cb2JlZtnAAJm4GkyaVKLef2XIlrqG PChan2LQlk49P15lqMXICglWzSPHAiy73bbPk9xr1eQwOMpLXE/O1XsewvgVuE4qrGNm ib5xEXYPxv6BkwScYd/yWc7Z+kMWyryKzYZOEROg0RhVZzeicMZabdvn+zVHeKXmrp/T PopUfxVkIHdu1/YI8mdVcuhRgvCBqGWISonFeydNYK1C9Hbr5QOsz9aI6oh3pn2VHi2f W7Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727687545; x=1728292345; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xp7nwUCJaW/bkSknjoRe7vWWzJDVDixFzfBIDbsBbN4=; b=WIYFlCSosXP6+bIUwgSZmNtNDV9j4oPzb/ShQlAlbwgl8YGJN1p2HyYI5dySF5MByi xJJakBJXMqGeUgJJh5cw1yoNG71m1/HUmtz6bFjN+56+BbZMHNTNpMXcHMd34MIPOGBH CAdtiz9F3e8b6IEJWDZY/BCjC0rqN0cRaEBUvRXtCVlZCNR6ZmwCZ30NdWnb3fGjp9qV Y6V3s3WlkupAkT/U2ID720GC39uNqPEGsrbbwZ7PELtw65OvBFRonB+3hiKBrF9qZiRX 9X9yEkuTR6KvwEx4o2JT2Mlox+o8bLiZsSnShQUXGpq/MiLrjELNgLNGaDmbz1vZvWdz lOLw== X-Gm-Message-State: AOJu0Yyka8oqBQQLz4XIUPhkyhiK3pus+n16QQb/9t1vZzz7Mv8vaaIm Bo4wVt8vfOFIn8sDIVrcGJhRw4P1VVsbIbiTR6c8ymC5BWK3ruX8/BqiPYnqM+PWyJE7Pl9fPd3 c X-Google-Smtp-Source: AGHT+IHvRdEPeY44ajJFKE6t3GBs8/tEavMd+4IYJeqCp6TUbQmrdfNCKixTO0T4rV7ABAE5is0PIg== X-Received: by 2002:a05:6000:d82:b0:37c:ca11:78c1 with SMTP id ffacd0b85a97d-37cd5ab7440mr5385294f8f.27.1727687545557; Mon, 30 Sep 2024 02:12:25 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson Subject: [PATCH 11/12] target/mips: Remove target-specific code in mips_cpu_reset_hold() Date: Mon, 30 Sep 2024 11:11:00 +0200 Message-ID: <20240930091101.40591-12-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930091101.40591-1-philmd@linaro.org> References: <20240930091101.40591-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727687564545116600 Since all code creating vCPUs now set the 'cpu-big-endian' property, we can remove the target-specific #ifdef'ry in mips_cpu_reset_hold(): the CP0C0_BE bit is set using the property cpu->is_big_endian value. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/cpu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 02e2e72f2d..9724e71a5e 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -202,9 +202,6 @@ static void mips_cpu_reset_hold(Object *obj, ResetType = type) env->CP0_PRid =3D env->cpu_model->CP0_PRid; env->CP0_Config0 =3D deposit32(env->cpu_model->CP0_Config0, CP0C0_BE, 1, cpu->is_big_endian); -#if TARGET_BIG_ENDIAN - env->CP0_Config0 |=3D (1 << CP0C0_BE); -#endif env->CP0_Config1 =3D env->cpu_model->CP0_Config1; env->CP0_Config2 =3D env->cpu_model->CP0_Config2; env->CP0_Config3 =3D env->cpu_model->CP0_Config3; --=20 2.45.2 From nobody Sat Dec 21 15:47:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727687621; cv=none; d=zohomail.com; s=zohoarc; b=kSGBKczVsAi+eveEOt0y8INKXxbv5xUKEX4W/ixNKS9SGo/txiMhqLoAZZ0QT3GC0651VrmqLehFdcyWENRkQBxaHhJ0uJP7y1rnUY9MUcIg6Z3aas0wh3WeVjxf7YQbEZbQgqoqFwI7Hbqy8+tDqyPjjdW4T8mBGSMEIcyj2j8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727687621; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EToKFctF2fRtYpb52soo3m8yr83BCZf/5mioMKUv2bg=; b=DCBAF4zNf8xz27bAKIlBdOwAqXFPoXEShz0M1RbM1HXCBZgu84ARFY2Bm24bAC5Usd8zkgcdhvR+5XQpnra8iDlxPcSuIYcHx/w5l72kbh2HyHpc48JFUfmN9fBdfR3nyfEYVL08JfM5uc8P5JIfIHPoNZg6yaceNnWouRtdg/4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727687621115634.7519748999343; Mon, 30 Sep 2024 02:13:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svCSM-00052h-Ku; Mon, 30 Sep 2024 05:12:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svCSK-0004kY-Cq for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:12:36 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svCSI-0004gh-OW for qemu-devel@nongnu.org; Mon, 30 Sep 2024 05:12:36 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-42cb9a0c300so31647385e9.0 for ; Mon, 30 Sep 2024 02:12:34 -0700 (PDT) Received: from localhost.localdomain (183.red-88-28-18.dynamicip.rima-tde.net. [88.28.18.183]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e96a52915sm144727645e9.39.2024.09.30.02.12.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 02:12:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727687552; x=1728292352; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EToKFctF2fRtYpb52soo3m8yr83BCZf/5mioMKUv2bg=; b=L8Y6AQHh799tW7TKo2t/YZQ6SB+Lso2wVe0mPLV/Sd0F8axe6JRotPqm59lcmIafbb 8bAawoc4VP9mnRR36YGpmhVdZZnZ7uq8ToxUuYO+bTdoOGhnaRt800mWZ8+3E2Kh/E1e tAw+C6RGKZZToC4wP0dPR+/C8CZR1CXoOyfJjUm6DFHNJgAXnzC4jZBxm6jj7pJUgy+6 CfZrnfy5Pxm47doyGLLjCV8Fy4z8JZS+A7GhINQBo6mWQxFL0nMaSe0tAZxmt8G4VSEt zpUeH7MvkkPOYzf/zv21bt47Por2ZYLvmcN0zjRsGVKTskKT6BE5xv8WdSy8TyLcU7UN KwtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727687552; x=1728292352; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EToKFctF2fRtYpb52soo3m8yr83BCZf/5mioMKUv2bg=; b=qskFoFVlTZum36JgkutnO3K2RdlyyZG1qslzXsBs5cWvs/eR3aMOq1U4ZbPKWzMf2G drLHUUEXqhNpWzSSsxtMVZqteY4q9GbWy8zRCjTXx4SxYLfFFzzAybA/qwUcFEwV5EZ+ dQDk5h8Kvnwrw5f3qxqCTa0Cobq9HG4/KlPZG51EwUECZKFZHi9xRgdWfX9YxXS7zvAW KkNt6bYlXvzOmvYqKrPvoD+rznSKA/UDmy3uPNqf7dXRDGykCXyURZ7vPZ39Cc/dR+P4 xbT9Z3ToBMtXM44zSUlPlcsYn7v0FI+jdjx8+s/Y5uR9RuFsVdOYKFd7shp0UKG1OKsU U/Cg== X-Gm-Message-State: AOJu0Yzr45Pn3bD7H/8yowpbb9HOa0PJvN7H8BMY68PTzVkBIDbjmVet XeB7Z73WUAs7rKohh3MAQtKDo5vvQ+H9aaREzxECrXklr8I3L32X87MTuaoB05+oqwAnIRls6Qg A X-Google-Smtp-Source: AGHT+IFNQ+dcllj3FH/1H792+7wbVFI2MZSpAoA7GTZoNegr+HAz4WlN3eoWFLqSIuVCmm04wDSc2Q== X-Received: by 2002:a05:600c:4751:b0:42c:de9b:a1b5 with SMTP id 5b1f17b1804b1-42f5849732amr77291775e9.32.1727687552382; Mon, 30 Sep 2024 02:12:32 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson Subject: [PATCH 12/12] hw/mips/malta: Remove TARGET_BIG_ENDIAN #ifdef'ry Date: Mon, 30 Sep 2024 11:11:01 +0200 Message-ID: <20240930091101.40591-13-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930091101.40591-1-philmd@linaro.org> References: <20240930091101.40591-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727687622984116600 Move code evaluation from preprocessor to compiler so the if() ladder is always processed. Mostly to unify style in not using TARGET_BIG_ENDIAN #ifdef anymore. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- hw/mips/malta.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 71cc11fc45..a3b6f63089 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1196,8 +1196,7 @@ void mips_malta_init(MachineState *machine) * In little endian mode the 32bit words in the bios are swapped, * a neat trick which allows bi-endian firmware. */ -#if !TARGET_BIG_ENDIAN - { + if (!TARGET_BIG_ENDIAN) { uint32_t *end, *addr; const size_t swapsize =3D MIN(bios_size, 0x3e0000); addr =3D rom_ptr(FLASH_ADDRESS, swapsize); @@ -1210,7 +1209,6 @@ void mips_malta_init(MachineState *machine) addr++; } } -#endif } =20 /* --=20 2.45.2