From nobody Sun Nov 24 02:29:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1727686487; cv=none; d=zohomail.com; s=zohoarc; b=V/pJ1EjoXARwd7SwrDDFlpbezD1C7ABXLTzX8NMDk4Cm+PEBxiNZu/WxBwRyeqO67GX3BXeHhQi8pZLWLb/l3bcKRLir7GyRMB7sMAy1J1HP1h/42tv1cNi6uEa4P2TVuedawPJHpLrFQqSgitWdNV2SfRorQWsDs9sRlmVOxnY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727686487; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=ZHNB4LxnvTXzka7dx5WtdJWxt+H+LF+Ncm8ahhP/gQk=; b=QbgjWIMs3OXpXGWhuJZzJujGzQdgEYdfN+Ayo7jHSmrD8MB5nqEYB9LNsd3lSJvKx8tOhg64dv1n1444+Hl4VpNH/YM1TFXf58DmUh/Azc+UXKq3zDy8L78eiLLfAvZNppebZn9LeDHspaqyhgLsKxi/3ahHmixZjyVaAJVDTlQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727686487290511.01023487134296; Mon, 30 Sep 2024 01:54:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svC9p-0005eM-EJ; Mon, 30 Sep 2024 04:53:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svC9Z-0004HH-Fc; Mon, 30 Sep 2024 04:53:18 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svC9W-00025U-BY; Mon, 30 Sep 2024 04:53:11 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 30 Sep 2024 16:52:41 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 30 Sep 2024 16:52:41 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Thomas Huth , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v6 8/8] hw/gpio/aspeed: Add test case for AST2700 Date: Mon, 30 Sep 2024 16:52:39 +0800 Message-ID: <20240930085239.3089901-9-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240930085239.3089901-1-jamin_lin@aspeedtech.com> References: <20240930085239.3089901-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1727686489311116600 Content-Type: text/plain; charset="utf-8" Add test case to test GPIO output and input pins from A0 to D7 for AST2700. Signed-off-by: Jamin Lin --- tests/qtest/aspeed_gpio-test.c | 77 ++++++++++++++++++++++++++++++++-- tests/qtest/meson.build | 3 ++ 2 files changed, 76 insertions(+), 4 deletions(-) diff --git a/tests/qtest/aspeed_gpio-test.c b/tests/qtest/aspeed_gpio-test.c index d38f51d719..03b3b1c2b2 100644 --- a/tests/qtest/aspeed_gpio-test.c +++ b/tests/qtest/aspeed_gpio-test.c @@ -33,6 +33,10 @@ #define GPIO_ABCD_DATA_VALUE 0x000 #define GPIO_ABCD_DIRECTION 0x004 =20 +/* AST2700 */ +#define AST2700_GPIO_BASE 0x14C0B000 +#define GPIOA0_CONTROL 0x180 + static void test_set_colocated_pins(const void *data) { QTestState *s =3D (QTestState *)data; @@ -72,17 +76,82 @@ static void test_set_input_pins(const void *data) g_assert_cmphex(value, =3D=3D, 0xffffffff); } =20 +static void test_2700_output_pins(const void *data) +{ + QTestState *s =3D (QTestState *)data; + uint32_t offset =3D 0; + uint32_t value =3D 0; + uint32_t pin =3D 0; + + for (char c =3D 'A'; c <=3D 'D'; c++) { + for (int i =3D 0; i < 8; i++) { + offset =3D AST2700_GPIO_BASE + GPIOA0_CONTROL + (pin * 4); + + /* output direction and output hi */ + qtest_writel(s, offset, 0x00000003); + value =3D qtest_readl(s, offset); + g_assert_cmphex(value, =3D=3D, 0x00000003); + + /* output direction and output low */ + qtest_writel(s, offset, 0x00000002); + value =3D qtest_readl(s, offset); + g_assert_cmphex(value, =3D=3D, 0x00000002); + pin++; + } + } +} + +static void test_2700_input_pins(const void *data) +{ + QTestState *s =3D (QTestState *)data; + char name[16]; + uint32_t offset =3D 0; + uint32_t value =3D 0; + uint32_t pin =3D 0; + + for (char c =3D 'A'; c <=3D 'D'; c++) { + for (int i =3D 0; i < 8; i++) { + sprintf(name, "gpio%c%d", c, i); + offset =3D AST2700_GPIO_BASE + GPIOA0_CONTROL + (pin * 4); + /* input direction */ + qtest_writel(s, offset, 0); + + /* set input */ + qtest_qom_set_bool(s, "/machine/soc/gpio", name, true); + value =3D qtest_readl(s, offset); + g_assert_cmphex(value, =3D=3D, 0x00002000); + + /* clear input */ + qtest_qom_set_bool(s, "/machine/soc/gpio", name, false); + value =3D qtest_readl(s, offset); + g_assert_cmphex(value, =3D=3D, 0); + pin++; + } + } +} + + int main(int argc, char **argv) { + const char *arch =3D qtest_get_arch(); QTestState *s; int r; =20 g_test_init(&argc, &argv, NULL); =20 - s =3D qtest_init("-machine ast2600-evb"); - qtest_add_data_func("/ast2600/gpio/set_colocated_pins", s, - test_set_colocated_pins); - qtest_add_data_func("/ast2600/gpio/set_input_pins", s, test_set_input_= pins); + if (strcmp(arch, "aarch64") =3D=3D 0) { + s =3D qtest_init("-machine ast2700-evb"); + qtest_add_data_func("/ast2700/gpio/input_pins", + s, test_2700_input_pins); + qtest_add_data_func("/ast2700/gpio/out_pins", s, test_2700_output_= pins); + } else { + s =3D qtest_init("-machine ast2600-evb"); + qtest_add_data_func("/ast2600/gpio/set_colocated_pins", s, + test_set_colocated_pins); + qtest_add_data_func("/ast2600/gpio/set_input_pins", s, + test_set_input_pins); + } + r =3D g_test_run(); qtest_quit(s); =20 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 310865e49c..292980e3ad 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -209,6 +209,8 @@ qtests_aspeed =3D \ ['aspeed_hace-test', 'aspeed_smc-test', 'aspeed_gpio-test'] +qtests_aspeed64 =3D \ + ['aspeed_gpio-test'] =20 qtests_stm32l4x5 =3D \ ['stm32l4x5_exti-test', @@ -247,6 +249,7 @@ qtests_aarch64 =3D \ (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test', 'bcm2= 835-i2c-test'] : []) + \ (config_all_accel.has_key('CONFIG_TCG') and = \ config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test']= : []) + \ + (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : [])= + \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', --=20 2.34.1