From nobody Sun Nov 24 03:40:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1727686447; cv=none; d=zohomail.com; s=zohoarc; b=C0CEqm9j4Drf3AXwl/XGEkDhmiD85SWL8yC0Y2DDVaIM4xhb4QhiJGca8eVmjPyFKvv7e9HpEo8URoBBK2e1X4yyUyBekuNvbt2F+KCeGO4aZBRNqT92xR2pyiBSEnCim8F3JZOsNn4tiX9UwiPToXfJEuCw9T87AkO/YoU+m6c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727686447; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=P7X2P7xC7BUNyYbRFwZ6RF4khGRcXt4YfmazKdKTwfs=; b=l36uB8adF63h1qIBwQ0m3shh/CnpMEBRuxMR6J4DrSinB91WzqAcNYDge+hkatCwZLHwJ1QOqP2CX+wuUhPd37YdkI/JpsyQDHoH0ac490TgY+fberbc7c9FZxX0XSanFcAfAVJcpMtCZCh/i8paLf96ic34hv/pOzlGI9MwKM8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17276864477131007.488664519053; Mon, 30 Sep 2024 01:54:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svC9h-0004Hs-12; Mon, 30 Sep 2024 04:53:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svC9K-0003FA-KN; Mon, 30 Sep 2024 04:52:59 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svC9I-00025U-AZ; Mon, 30 Sep 2024 04:52:58 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 30 Sep 2024 16:52:40 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 30 Sep 2024 16:52:40 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Thomas Huth , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v6 3/8] hw/gpio/aspeed: Support different memory region ops Date: Mon, 30 Sep 2024 16:52:34 +0800 Message-ID: <20240930085239.3089901-4-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240930085239.3089901-1-jamin_lin@aspeedtech.com> References: <20240930085239.3089901-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1727686449338116600 It set "aspeed_gpio_ops" struct which containing read and write callbacks to be used when I/O is performed on the GPIO region. Besides, in the previous design of ASPEED SOCs, one register is used for setting one function for 32 GPIO pins. ex: GPIO000 is used for setting data value for GPIO A, B, C and D in AST260= 0. ex: GPIO004 is used for setting direction for GPIO A, B, C and D in AST2600. However, the register set have a significant change in AST2700. Each GPIO pin has their own control register. In other words, users are abl= e to set one GPIO pin=E2=80=99s direction, interrupt enable, input mask and so on in one register. The aspeed_gpio_read/aspeed_gpio_write callback functions are not compatible AST2700. Introduce a new "const MemoryRegionOps *" attribute in AspeedGPIOClass and use it in aspeed_gpio_realize function. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/gpio/aspeed_gpio.c | 7 ++++++- include/hw/gpio/aspeed_gpio.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index 564459ad4f..8725606aec 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -1046,7 +1046,7 @@ static void aspeed_gpio_realize(DeviceState *dev, Err= or **errp) } } =20 - memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s, + memory_region_init_io(&s->iomem, OBJECT(s), agc->reg_ops, s, TYPE_ASPEED_GPIO, agc->mem_size); =20 sysbus_init_mmio(sbd, &s->iomem); @@ -1131,6 +1131,7 @@ static void aspeed_gpio_ast2400_class_init(ObjectClas= s *klass, void *data) agc->reg_table =3D aspeed_3_3v_gpios; agc->reg_table_count =3D GPIO_3_3V_REG_ARRAY_SIZE; agc->mem_size =3D 0x1000; + agc->reg_ops =3D &aspeed_gpio_ops; } =20 static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) @@ -1143,6 +1144,7 @@ static void aspeed_gpio_2500_class_init(ObjectClass *= klass, void *data) agc->reg_table =3D aspeed_3_3v_gpios; agc->reg_table_count =3D GPIO_3_3V_REG_ARRAY_SIZE; agc->mem_size =3D 0x1000; + agc->reg_ops =3D &aspeed_gpio_ops; } =20 static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *= data) @@ -1155,6 +1157,7 @@ static void aspeed_gpio_ast2600_3_3v_class_init(Objec= tClass *klass, void *data) agc->reg_table =3D aspeed_3_3v_gpios; agc->reg_table_count =3D GPIO_3_3V_REG_ARRAY_SIZE; agc->mem_size =3D 0x800; + agc->reg_ops =3D &aspeed_gpio_ops; } =20 static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *= data) @@ -1167,6 +1170,7 @@ static void aspeed_gpio_ast2600_1_8v_class_init(Objec= tClass *klass, void *data) agc->reg_table =3D aspeed_1_8v_gpios; agc->reg_table_count =3D GPIO_1_8V_REG_ARRAY_SIZE; agc->mem_size =3D 0x800; + agc->reg_ops =3D &aspeed_gpio_ops; } =20 static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data) @@ -1179,6 +1183,7 @@ static void aspeed_gpio_1030_class_init(ObjectClass *= klass, void *data) agc->reg_table =3D aspeed_3_3v_gpios; agc->reg_table_count =3D GPIO_3_3V_REG_ARRAY_SIZE; agc->mem_size =3D 0x1000; + agc->reg_ops =3D &aspeed_gpio_ops; } =20 static const TypeInfo aspeed_gpio_info =3D { diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h index 8cd2ff5496..e1e6c54333 100644 --- a/include/hw/gpio/aspeed_gpio.h +++ b/include/hw/gpio/aspeed_gpio.h @@ -77,6 +77,7 @@ struct AspeedGPIOClass { const AspeedGPIOReg *reg_table; unsigned reg_table_count; uint64_t mem_size; + const MemoryRegionOps *reg_ops; }; =20 struct AspeedGPIOState { --=20 2.34.1