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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 05/13] hw/mips: Add cpu_is_bigendian field to BlCpuCfg structure Date: Mon, 30 Sep 2024 09:34:42 +0200 Message-ID: <20240930073450.33195-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727683532359116600 Add the BlCpuCfg::cpu_is_bigendian field, initialize it in machine code. Bootloader API use the ld/st_endian_p() to dispatch to target endianness. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/hw/mips/bootloader.h | 1 + hw/mips/bootloader.c | 10 +++++----- hw/mips/boston.c | 2 +- hw/mips/fuloong2e.c | 2 +- hw/mips/malta.c | 2 +- 5 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index 744eb11d0e..ef778a38d0 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -13,6 +13,7 @@ #include "exec/target_long.h" =20 typedef struct bl_cpu_cfg { + bool cpu_is_bigendian; } BlCpuCfg; =20 void bl_gen_jump_to(const BlCpuCfg *cfg, void **p, target_ulong jump_addr); diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index ee1a1c4f20..258cc5d8c8 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -58,9 +58,9 @@ static void st_nm32_p(const BlCpuCfg *cfg, void **ptr, ui= nt32_t insn) { uint16_t *p =3D *ptr; =20 - stw_p(p, insn >> 16); + stw_endian_p(cfg->cpu_is_bigendian, p, insn >> 16); p++; - stw_p(p, insn >> 0); + stw_endian_p(cfg->cpu_is_bigendian, p, insn >> 0); p++; =20 *ptr =3D p; @@ -74,7 +74,7 @@ static void bl_gen_nop(const BlCpuCfg *cfg, void **ptr) } else { uint32_t *p =3D *ptr; =20 - stl_p(p, 0); + stl_endian_p(cfg->cpu_is_bigendian, p, 0); p++; *ptr =3D p; } @@ -95,7 +95,7 @@ static void bl_gen_r_type(const BlCpuCfg *cfg, insn =3D deposit32(insn, 6, 5, shift); insn =3D deposit32(insn, 0, 6, funct); =20 - stl_p(p, insn); + stl_endian_p(cfg->cpu_is_bigendian, p, insn); p++; =20 *ptr =3D p; @@ -113,7 +113,7 @@ static void bl_gen_i_type(const BlCpuCfg *cfg, insn =3D deposit32(insn, 16, 5, rt); insn =3D deposit32(insn, 0, 16, imm); =20 - stl_p(p, insn); + stl_endian_p(cfg->cpu_is_bigendian, p, insn); p++; =20 *ptr =3D p; diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 8e210876e1..d4dd242d0d 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -325,7 +325,7 @@ type_init(boston_register_types) =20 static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) { - const BlCpuCfg bl_cfg =3D { }; + const BlCpuCfg bl_cfg =3D { .cpu_is_bigendian =3D TARGET_BIG_ENDIAN }; uint64_t regaddr; =20 /* Move CM GCRs */ diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index a989637d3b..4fe5108845 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -165,7 +165,7 @@ static uint64_t load_kernel(MIPSCPU *cpu) static void write_bootloader(CPUMIPSState *env, uint8_t *base, uint64_t kernel_addr) { - const BlCpuCfg bl_cfg =3D { }; + const BlCpuCfg bl_cfg =3D { .cpu_is_bigendian =3D false }; uint32_t *p; =20 /* Small bootloader */ diff --git a/hw/mips/malta.c b/hw/mips/malta.c index fc485cc884..6e73c896ff 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -624,7 +624,7 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint= 64_t run_addr, static const char pci_pins_cfg[PCI_NUM_PINS] =3D { 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ }; - const BlCpuCfg bl_cfg =3D { }; + const BlCpuCfg bl_cfg =3D { .cpu_is_bigendian =3D TARGET_BIG_ENDIAN }; =20 /* Bus endianness is always reversed */ #if TARGET_BIG_ENDIAN --=20 2.45.2