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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 01/13] qemu/bswap: Introduce ld/st_endian_p() API Date: Mon, 30 Sep 2024 09:34:38 +0200 Message-ID: <20240930073450.33195-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philmd@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727683297394116600 Introduce the ld/st_endian_p() API, which takes an extra boolean argument to dispatch to ld/st_{be,le}_p() methods. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- TODO: Update docstring regexp --- include/qemu/bswap.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index ad22910a5d..ec813a756d 100644 --- a/include/qemu/bswap.h +++ b/include/qemu/bswap.h @@ -433,4 +433,23 @@ DO_STN_LDN_P(be) #undef le_bswaps #undef be_bswaps =20 +#define lduw_endian_p(big_endian, p) \ + (big_endian) ? lduw_be_p(p) : lduw_le_p(p) +#define ldsw_endian_p(big_endian, p) \ + (big_endian) ? ldsw_be_p(p) : ldsw_be_p(p) +#define ldl_endian_p(big_endian, p) \ + (big_endian) ? ldl_be_p(p) : ldl_le_p(p) +#define ldq_endian_p(big_endian, p) \ + (big_endian) ? ldq_be_p(p) : ldq_le_p(p) +#define stw_endian_p(big_endian, p, v) \ + (big_endian) ? stw_be_p(p, v) : stw_le_p(p, v) +#define stl_endian_p(big_endian, p, v) \ + (big_endian) ? stl_be_p(p, v) : stl_le_p(p, v) +#define stq_endian_p(big_endian, p, v) \ + (big_endian) ? stq_be_p(p, v) : stq_le_p(p, v) +#define ldn_endian_p(big_endian, p, sz) \ + (big_endian) ? ldn_be_p(p, sz) : ldn_le_p(p, sz) +#define stn_endian_p(big_endian, p, sz, v) \ + (big_endian) ? stn_be_p(p, sz, v) : stn_le_p(p, sz, v) + #endif /* BSWAP_H */ --=20 2.45.2 From nobody Sun Nov 24 00:26:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727683377; cv=none; d=zohomail.com; s=zohoarc; b=k4ewj4Tytzi6b8lEGIu37cUvLaXtMjLYoFbSexxi9qhsi4NndClUr/0oxQkmtHVwFSDilaNIBEKvHdp65oazsQZbu5lw+F5aFcJaPkSfTdgCrQCActKxUDj6T6N4+ehcaCfWwdRYoKSLsqxvtUNWRiylFrUvNfRfmnpA789s+fQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727683377; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=yXipE1vCqUL/2GGIC/pfDOg0/7HE+1Efkqb3qV24aq0=; b=Ot4YlN3O1sFn7pf4qu/cf/si9PVQfY26asdKJWT4HpqK12MqgptvXLw82n/woTVb0Qhua06HGL92hZjEalFjXcNmDJPZHsjB/AAoW6CGZCPbYrHvNIum5ncrdKS0yMUP3n6WLp+k+f4ObFnfKlXiQBdz87kB5hbNNDjS8KVROBE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727683377718442.98191290805926; Mon, 30 Sep 2024 01:02:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svBMp-0003f4-5v; Mon, 30 Sep 2024 04:02:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svBMe-00035X-T6 for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:02:42 -0400 Received: from mail-lj1-x232.google.com ([2a00:1450:4864:20::232]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svBMd-0003rQ-49 for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:02:40 -0400 Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2f75c56f16aso48037901fa.0 for ; Mon, 30 Sep 2024 01:02:38 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 02/13] hw/virtio/virtio-access: Use the ld/st_endian_p() API Date: Mon, 30 Sep 2024 09:34:39 +0200 Message-ID: <20240930073450.33195-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=philmd@linaro.org; helo=mail-lj1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727683379647116600 Refactor to use the recently introduced ld/st_endian_p() API No logical change intended. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/hw/virtio/virtio-access.h | 36 ++++++------------------------- 1 file changed, 6 insertions(+), 30 deletions(-) diff --git a/include/hw/virtio/virtio-access.h b/include/hw/virtio/virtio-a= ccess.h index 07aae69042..b920874be8 100644 --- a/include/hw/virtio/virtio-access.h +++ b/include/hw/virtio/virtio-access.h @@ -95,56 +95,32 @@ static inline void virtio_stl_phys(VirtIODevice *vdev, = hwaddr pa, =20 static inline void virtio_stw_p(VirtIODevice *vdev, void *ptr, uint16_t v) { - if (virtio_access_is_big_endian(vdev)) { - stw_be_p(ptr, v); - } else { - stw_le_p(ptr, v); - } + stw_endian_p(virtio_access_is_big_endian(vdev), ptr, v); } =20 static inline void virtio_stl_p(VirtIODevice *vdev, void *ptr, uint32_t v) { - if (virtio_access_is_big_endian(vdev)) { - stl_be_p(ptr, v); - } else { - stl_le_p(ptr, v); - } + stl_endian_p(virtio_access_is_big_endian(vdev), ptr, v); } =20 static inline void virtio_stq_p(VirtIODevice *vdev, void *ptr, uint64_t v) { - if (virtio_access_is_big_endian(vdev)) { - stq_be_p(ptr, v); - } else { - stq_le_p(ptr, v); - } + stq_endian_p(virtio_access_is_big_endian(vdev), ptr, v); } =20 static inline int virtio_lduw_p(VirtIODevice *vdev, const void *ptr) { - if (virtio_access_is_big_endian(vdev)) { - return lduw_be_p(ptr); - } else { - return lduw_le_p(ptr); - } + return lduw_endian_p(virtio_access_is_big_endian(vdev), ptr); } =20 static inline int virtio_ldl_p(VirtIODevice *vdev, const void *ptr) { - if (virtio_access_is_big_endian(vdev)) { - return ldl_be_p(ptr); - } else { - return ldl_le_p(ptr); - } + return ldl_endian_p(virtio_access_is_big_endian(vdev), ptr); } =20 static inline uint64_t virtio_ldq_p(VirtIODevice *vdev, const void *ptr) { - if (virtio_access_is_big_endian(vdev)) { - return ldq_be_p(ptr); - } else { - return ldq_le_p(ptr); - } + return ldq_endian_p(virtio_access_is_big_endian(vdev), ptr); } =20 static inline uint16_t virtio_tswap16(VirtIODevice *vdev, uint16_t s) --=20 2.45.2 From nobody Sun Nov 24 00:26:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727683635; cv=none; d=zohomail.com; s=zohoarc; b=JK6SfcWAVpguYShmLPjxtmU0FQPMyjMfZHCv+HF250P2DlZGby9jpHc+Y44OQ32og3UclOGP0hUviZ+Awct2EMRjHpCvTHyZs/iM4AnFaEpO2Poev/ICeofKJsTediI3S30jN5inBMvjPyXoU/fvY/aqZmmMSIie9SEJD9rWrj4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727683635; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PDKmxhtETyeu/iYuY2neXJ4cpuVufAHpcFENKpKvuEg=; b=f51vjNjJeQos55lIIdnrjUU8KXRzFuWsaqPvCgURcmlIkKElnThzvogTB0eXtkQTj2mMnbW8uSFTEnLwsdFtzGIYuotyXWYlc2rPr/HuSO7AwUqVhEKsKETr52ZkabdWyllJG71SNd4DYqhmLOO7C1YQdeYzCpbxl4Dnw85A1D4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727683635061177.26835076550844; Mon, 30 Sep 2024 01:07:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svBQs-0002Gt-Qf; Mon, 30 Sep 2024 04:07:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svBQq-00022k-T9 for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:07:01 -0400 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svBQp-0004Zw-0r for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:07:00 -0400 Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-a8a7cdfdd80so675769966b.0 for ; Mon, 30 Sep 2024 01:06:58 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 03/13] target/arm/ptw: Use the ld/st_endian_p() API Date: Mon, 30 Sep 2024 09:34:40 +0200 Message-ID: <20240930073450.33195-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philmd@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727683636347116600 Refactor to use the recently introduced ld/st_endian_p() API No logical change intended. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/ptw.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index defd6b84de..a1a6b1fec3 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -699,11 +699,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Transl= ate *ptw, data =3D le64_to_cpu(data); } #else - if (ptw->out_be) { - data =3D ldq_be_p(host); - } else { - data =3D ldq_le_p(host); - } + data =3D ldq_endian_p(ptw->out_be, host); #endif } else { /* Page tables are in MMIO. */ @@ -860,16 +856,9 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_= t old_val, if (!locked) { bql_lock(); } - if (ptw->out_be) { - cur_val =3D ldq_be_p(host); - if (cur_val =3D=3D old_val) { - stq_be_p(host, new_val); - } - } else { - cur_val =3D ldq_le_p(host); - if (cur_val =3D=3D old_val) { - stq_le_p(host, new_val); - } + cur_val =3D ldq_endian_p(ptw->out_be, host); + if (cur_val =3D=3D old_val) { + stq_endian_p(ptw->out_be, host, new_val); } if (!locked) { bql_unlock(); --=20 2.45.2 From nobody Sun Nov 24 00:26:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727683175; cv=none; d=zohomail.com; s=zohoarc; b=kQ9BLtLyQHFJhCkD0e4tsr4v8h2WcbGXeXUTwUo2q7MuN7IwfzHWIPorSfLPnO2k5a9kloAVXEv901/YYApMFM4xOi4D93pURg5aQU61ssDQtRNXDOYty10ijF4RwMxZuKKPbZW/wbdhwoUXvnujXu1eBCF5SD8KcTD2v+z69Sc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727683175; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xlB7TER95AHLu1cUEZk4SLXmuphORdTbB9q557qt3nU=; b=HclFb2dhtH1F+Pp0sF7rCGSwkUY43q3gsAxi0dD1LH0z8BO/Y5TdRwjGbRGEouuk9g0g9XdwWz20bF7UbzXYojv/WsXeDDo7OGMsHQnsds9UTX5/WLikJe5gnXp9pctxuHtXm9LFijdmtSlA47Lt07N0aXPmLnA3QxuImPymwec= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727683175511183.6343229346503; Mon, 30 Sep 2024 00:59:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svAzG-00049A-1M; Mon, 30 Sep 2024 03:38:32 -0400 Received: from [2001:470:142:3::10] (helo=eggs.gnu.org) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svAz3-00040e-Rn for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:38:23 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svAxu-0008Kw-3b for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:37:56 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-3770320574aso2669508f8f.2 for ; Mon, 30 Sep 2024 00:35:46 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 04/13] hw/mips: Pass BlCpuCfg argument to bootloader API Date: Mon, 30 Sep 2024 09:34:41 +0200 Message-ID: <20240930073450.33195-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727683176935116600 In preparation to pass endianness and target word size to the bootloader API, introduce an empty BlCpuCfg structure and propagate it to the MIPS bootloader methods. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/hw/mips/bootloader.h | 17 +++-- hw/mips/bootloader.c | 142 +++++++++++++++++++---------------- hw/mips/boston.c | 9 ++- hw/mips/fuloong2e.c | 3 +- hw/mips/malta.c | 21 +++--- 5 files changed, 109 insertions(+), 83 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index c32f6c2835..744eb11d0e 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -10,17 +10,24 @@ #define HW_MIPS_BOOTLOADER_H =20 #include "exec/cpu-defs.h" +#include "exec/target_long.h" =20 -void bl_gen_jump_to(void **ptr, target_ulong jump_addr); -void bl_gen_jump_kernel(void **ptr, +typedef struct bl_cpu_cfg { +} BlCpuCfg; + +void bl_gen_jump_to(const BlCpuCfg *cfg, void **p, target_ulong jump_addr); +void bl_gen_jump_kernel(const BlCpuCfg *cfg, void **ptr, bool set_sp, target_ulong sp, bool set_a0, target_ulong a0, bool set_a1, target_ulong a1, bool set_a2, target_ulong a2, bool set_a3, target_ulong a3, target_ulong kernel_addr); -void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val); -void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val); -void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val); +void bl_gen_write_ulong(const BlCpuCfg *cfg, void **ptr, + target_ulong addr, target_ulong val); +void bl_gen_write_u32(const BlCpuCfg *cfg, void **ptr, + target_ulong addr, uint32_t val); +void bl_gen_write_u64(const BlCpuCfg *cfg, void **ptr, + target_ulong addr, uint64_t val); =20 #endif diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 1dd6ef2096..ee1a1c4f20 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -54,7 +54,7 @@ static bool bootcpu_supports_isa(uint64_t isa_mask) return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask); } =20 -static void st_nm32_p(void **ptr, uint32_t insn) +static void st_nm32_p(const BlCpuCfg *cfg, void **ptr, uint32_t insn) { uint16_t *p =3D *ptr; =20 @@ -67,10 +67,10 @@ static void st_nm32_p(void **ptr, uint32_t insn) } =20 /* Base types */ -static void bl_gen_nop(void **ptr) +static void bl_gen_nop(const BlCpuCfg *cfg, void **ptr) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { - st_nm32_p(ptr, 0x8000c000); + st_nm32_p(cfg, ptr, 0x8000c000); } else { uint32_t *p =3D *ptr; =20 @@ -80,7 +80,8 @@ static void bl_gen_nop(void **ptr) } } =20 -static void bl_gen_r_type(void **ptr, uint8_t opcode, +static void bl_gen_r_type(const BlCpuCfg *cfg, + void **ptr, uint8_t opcode, bl_reg rs, bl_reg rt, bl_reg rd, uint8_t shift, uint8_t funct) { @@ -100,7 +101,8 @@ static void bl_gen_r_type(void **ptr, uint8_t opcode, *ptr =3D p; } =20 -static void bl_gen_i_type(void **ptr, uint8_t opcode, +static void bl_gen_i_type(const BlCpuCfg *cfg, + void **ptr, uint8_t opcode, bl_reg rs, bl_reg rt, uint16_t imm) { uint32_t *p =3D *ptr; @@ -118,16 +120,17 @@ static void bl_gen_i_type(void **ptr, uint8_t opcode, } =20 /* Single instructions */ -static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa) +static void bl_gen_dsll(const BlCpuCfg *cfg, void **p, + bl_reg rd, bl_reg rt, uint8_t sa) { if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38); + bl_gen_r_type(cfg, p, 0, 0, rt, rd, sa, 0x38); } else { g_assert_not_reached(); /* unsupported */ } } =20 -static void bl_gen_jalr(void **p, bl_reg rs) +static void bl_gen_jalr(const BlCpuCfg *cfg, void **p, bl_reg rs) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { uint32_t insn =3D 0; @@ -136,13 +139,14 @@ static void bl_gen_jalr(void **p, bl_reg rs) insn =3D deposit32(insn, 21, 5, BL_REG_RA); insn =3D deposit32(insn, 16, 5, rs); =20 - st_nm32_p(p, insn); + st_nm32_p(cfg, p, insn); } else { - bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09); + bl_gen_r_type(cfg, p, 0, rs, 0, BL_REG_RA, 0, 0x09); } } =20 -static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20) +static void bl_gen_lui_nm(const BlCpuCfg *cfg, void **ptr, + bl_reg rt, uint32_t imm20) { uint32_t insn =3D 0; =20 @@ -153,16 +157,18 @@ static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint= 32_t imm20) insn =3D deposit32(insn, 2, 10, extract32(imm20, 9, 10)); insn =3D deposit32(insn, 0, 1, sextract32(imm20, 19, 1)); =20 - st_nm32_p(ptr, insn); + st_nm32_p(cfg, ptr, insn); } =20 -static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm) +static void bl_gen_lui(const BlCpuCfg *cfg, void **p, + bl_reg rt, uint16_t imm) { /* R6: It's a alias of AUI with RS =3D 0 */ - bl_gen_i_type(p, 0x0f, 0, rt, imm); + bl_gen_i_type(cfg, p, 0x0f, 0, rt, imm); } =20 -static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t imm12) +static void bl_gen_ori_nm(const BlCpuCfg *cfg, void **ptr, + bl_reg rt, bl_reg rs, uint16_t imm12) { uint32_t insn =3D 0; =20 @@ -172,15 +178,17 @@ static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_r= eg rs, uint16_t imm12) insn =3D deposit32(insn, 16, 5, rs); insn =3D deposit32(insn, 0, 12, imm12); =20 - st_nm32_p(ptr, insn); + st_nm32_p(cfg, ptr, insn); } =20 -static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm) +static void bl_gen_ori(const BlCpuCfg *cfg, void **p, + bl_reg rt, bl_reg rs, uint16_t imm) { - bl_gen_i_type(p, 0x0d, rs, rt, imm); + bl_gen_i_type(cfg, p, 0x0d, rs, rt, imm); } =20 -static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12) +static void bl_gen_sw_nm(const BlCpuCfg *cfg, void **ptr, + bl_reg rt, uint8_t rs, uint16_t ofs12) { uint32_t insn =3D 0; =20 @@ -191,66 +199,71 @@ static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8= _t rs, uint16_t ofs12) insn =3D deposit32(insn, 12, 4, 0b1001); insn =3D deposit32(insn, 0, 12, ofs12); =20 - st_nm32_p(ptr, insn); + st_nm32_p(cfg, ptr, insn); } =20 -static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset) +static void bl_gen_sw(const BlCpuCfg *cfg, void **p, + bl_reg rt, uint8_t base, uint16_t offset) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { - bl_gen_sw_nm(p, rt, base, offset); + bl_gen_sw_nm(cfg, p, rt, base, offset); } else { - bl_gen_i_type(p, 0x2b, base, rt, offset); + bl_gen_i_type(cfg, p, 0x2b, base, rt, offset); } } =20 -static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset) +static void bl_gen_sd(const BlCpuCfg *cfg, void **p, + bl_reg rt, uint8_t base, uint16_t offset) { if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_i_type(p, 0x3f, base, rt, offset); + bl_gen_i_type(cfg, p, 0x3f, base, rt, offset); } else { g_assert_not_reached(); /* unsupported */ } } =20 /* Pseudo instructions */ -static void bl_gen_li(void **p, bl_reg rt, uint32_t imm) +static void bl_gen_li(const BlCpuCfg *cfg, void **p, + bl_reg rt, uint32_t imm) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { - bl_gen_lui_nm(p, rt, extract32(imm, 12, 20)); - bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12)); + bl_gen_lui_nm(cfg, p, rt, extract32(imm, 12, 20)); + bl_gen_ori_nm(cfg, p, rt, rt, extract32(imm, 0, 12)); } else { - bl_gen_lui(p, rt, extract32(imm, 16, 16)); - bl_gen_ori(p, rt, rt, extract32(imm, 0, 16)); + bl_gen_lui(cfg, p, rt, extract32(imm, 16, 16)); + bl_gen_ori(cfg, p, rt, rt, extract32(imm, 0, 16)); } } =20 -static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm) +static void bl_gen_dli(const BlCpuCfg *cfg, void **p, + bl_reg rt, uint64_t imm) { - bl_gen_li(p, rt, extract64(imm, 32, 32)); - bl_gen_dsll(p, rt, rt, 16); - bl_gen_ori(p, rt, rt, extract64(imm, 16, 16)); - bl_gen_dsll(p, rt, rt, 16); - bl_gen_ori(p, rt, rt, extract64(imm, 0, 16)); + bl_gen_li(cfg, p, rt, extract64(imm, 32, 32)); + bl_gen_dsll(cfg, p, rt, rt, 16); + bl_gen_ori(cfg, p, rt, rt, extract64(imm, 16, 16)); + bl_gen_dsll(cfg, p, rt, rt, 16); + bl_gen_ori(cfg, p, rt, rt, extract64(imm, 0, 16)); } =20 -static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm) +static void bl_gen_load_ulong(const BlCpuCfg *cfg, void **p, + bl_reg rt, target_ulong imm) { if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_dli(p, rt, imm); /* 64bit */ + bl_gen_dli(cfg, p, rt, imm); /* 64bit */ } else { - bl_gen_li(p, rt, imm); /* 32bit */ + bl_gen_li(cfg, p, rt, imm); /* 32bit */ } } =20 /* Helpers */ -void bl_gen_jump_to(void **p, target_ulong jump_addr) +void bl_gen_jump_to(const BlCpuCfg *cfg, void **p, target_ulong jump_addr) { - bl_gen_load_ulong(p, BL_REG_T9, jump_addr); - bl_gen_jalr(p, BL_REG_T9); - bl_gen_nop(p); /* delay slot */ + bl_gen_load_ulong(cfg, p, BL_REG_T9, jump_addr); + bl_gen_jalr(cfg, p, BL_REG_T9); + bl_gen_nop(cfg, p); /* delay slot */ } =20 -void bl_gen_jump_kernel(void **p, +void bl_gen_jump_kernel(const BlCpuCfg *cfg, void **p, bool set_sp, target_ulong sp, bool set_a0, target_ulong a0, bool set_a1, target_ulong a1, @@ -259,45 +272,48 @@ void bl_gen_jump_kernel(void **p, target_ulong kernel_addr) { if (set_sp) { - bl_gen_load_ulong(p, BL_REG_SP, sp); + bl_gen_load_ulong(cfg, p, BL_REG_SP, sp); } if (set_a0) { - bl_gen_load_ulong(p, BL_REG_A0, a0); + bl_gen_load_ulong(cfg, p, BL_REG_A0, a0); } if (set_a1) { - bl_gen_load_ulong(p, BL_REG_A1, a1); + bl_gen_load_ulong(cfg, p, BL_REG_A1, a1); } if (set_a2) { - bl_gen_load_ulong(p, BL_REG_A2, a2); + bl_gen_load_ulong(cfg, p, BL_REG_A2, a2); } if (set_a3) { - bl_gen_load_ulong(p, BL_REG_A3, a3); + bl_gen_load_ulong(cfg, p, BL_REG_A3, a3); } =20 - bl_gen_jump_to(p, kernel_addr); + bl_gen_jump_to(cfg, p, kernel_addr); } =20 -void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) +void bl_gen_write_ulong(const BlCpuCfg *cfg, void **p, + target_ulong addr, target_ulong val) { - bl_gen_load_ulong(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); + bl_gen_load_ulong(cfg, p, BL_REG_K0, val); + bl_gen_load_ulong(cfg, p, BL_REG_K1, addr); if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sd(cfg, p, BL_REG_K0, BL_REG_K1, 0x0); } else { - bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sw(cfg, p, BL_REG_K0, BL_REG_K1, 0x0); } } =20 -void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val) +void bl_gen_write_u32(const BlCpuCfg *cfg, void **p, + target_ulong addr, uint32_t val) { - bl_gen_li(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); - bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_li(cfg, p, BL_REG_K0, val); + bl_gen_load_ulong(cfg, p, BL_REG_K1, addr); + bl_gen_sw(cfg, p, BL_REG_K0, BL_REG_K1, 0x0); } =20 -void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val) +void bl_gen_write_u64(const BlCpuCfg *cfg, void **p, + target_ulong addr, uint64_t val) { - bl_gen_dli(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); - bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_dli(cfg, p, BL_REG_K0, val); + bl_gen_load_ulong(cfg, p, BL_REG_K1, addr); + bl_gen_sd(cfg, p, BL_REG_K0, BL_REG_K1, 0x0); } diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 1b44fb354c..8e210876e1 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -325,23 +325,24 @@ type_init(boston_register_types) =20 static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) { + const BlCpuCfg bl_cfg =3D { }; uint64_t regaddr; =20 /* Move CM GCRs */ regaddr =3D cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, + bl_gen_write_ulong(&bl_cfg, &p, regaddr, boston_memmap[BOSTON_CM].base); =20 /* Move & enable GIC GCRs */ regaddr =3D cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_GIC_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, + bl_gen_write_ulong(&bl_cfg, &p, regaddr, boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN= _MSK); =20 /* Move & enable CPC GCRs */ regaddr =3D cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_CPC_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, + bl_gen_write_ulong(&bl_cfg, &p, regaddr, boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN= _MSK); =20 /* @@ -352,7 +353,7 @@ static void gen_firmware(void *p, hwaddr kernel_entry, = hwaddr fdt_addr) * a2/$6 =3D 0 * a3/$7 =3D 0 */ - bl_gen_jump_kernel(&p, + bl_gen_jump_kernel(&bl_cfg, &p, true, 0, true, (int32_t)-2, true, fdt_addr, true, 0, true, 0, kernel_entry); diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 6e4303ba47..a989637d3b 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -165,6 +165,7 @@ static uint64_t load_kernel(MIPSCPU *cpu) static void write_bootloader(CPUMIPSState *env, uint8_t *base, uint64_t kernel_addr) { + const BlCpuCfg bl_cfg =3D { }; uint32_t *p; =20 /* Small bootloader */ @@ -178,7 +179,7 @@ static void write_bootloader(CPUMIPSState *env, uint8_t= *base, /* Second part of the bootloader */ p =3D (uint32_t *)(base + 0x040); =20 - bl_gen_jump_kernel((void **)&p, + bl_gen_jump_kernel(&bl_cfg, (void **)&p, true, ENVP_VADDR - 64, true, 2, true, ENVP_VADDR, true, ENVP_VADDR + 8, diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 664a2ae0a9..fc485cc884 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -624,6 +624,7 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint= 64_t run_addr, static const char pci_pins_cfg[PCI_NUM_PINS] =3D { 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ }; + const BlCpuCfg bl_cfg =3D { }; =20 /* Bus endianness is always reversed */ #if TARGET_BIG_ENDIAN @@ -635,29 +636,29 @@ static void bl_setup_gt64120_jump_kernel(void **p, ui= nt64_t run_addr, /* setup MEM-to-PCI0 mapping as done by YAMON */ =20 /* move GT64120 registers from 0x14000000 to 0x1be00000 */ - bl_gen_write_u32(p, /* GT_ISD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_ISD */ cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68), cpu_to_gt32(0x1be00000 << 3)); =20 /* setup PCI0 io window to 0x18000000-0x181fffff */ - bl_gen_write_u32(p, /* GT_PCI0IOLD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0IOLD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48), cpu_to_gt32(0x18000000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0IOHD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0IOHD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50), cpu_to_gt32(0x08000000 << 3)); =20 /* setup PCI0 mem windows */ - bl_gen_write_u32(p, /* GT_PCI0M0LD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0M0LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58), cpu_to_gt32(0x10000000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M0HD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0M0HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60), cpu_to_gt32(0x07e00000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M1LD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0M1LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80), cpu_to_gt32(0x18200000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M1HD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0M1HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88), cpu_to_gt32(0x0bc00000 << 3)); =20 @@ -668,16 +669,16 @@ static void bl_setup_gt64120_jump_kernel(void **p, ui= nt64_t run_addr, * Load the PIIX IRQC[A:D] routing config address, then * write routing configuration to the config data register. */ - bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0_CFGADDR */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), tswap32((1 << 31) /* ConfigEn */ | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 | PIIX_PIRQCA)); - bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0_CFGDATA */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), tswap32(ldl_be_p(pci_pins_cfg))); =20 - bl_gen_jump_kernel(p, + bl_gen_jump_kernel(&bl_cfg, p, true, ENVP_VADDR - 64, /* * If semihosting is used, arguments have already --=20 2.45.2 From nobody Sun Nov 24 00:26:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 05/13] hw/mips: Add cpu_is_bigendian field to BlCpuCfg structure Date: Mon, 30 Sep 2024 09:34:42 +0200 Message-ID: <20240930073450.33195-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727683532359116600 Add the BlCpuCfg::cpu_is_bigendian field, initialize it in machine code. Bootloader API use the ld/st_endian_p() to dispatch to target endianness. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/hw/mips/bootloader.h | 1 + hw/mips/bootloader.c | 10 +++++----- hw/mips/boston.c | 2 +- hw/mips/fuloong2e.c | 2 +- hw/mips/malta.c | 2 +- 5 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index 744eb11d0e..ef778a38d0 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -13,6 +13,7 @@ #include "exec/target_long.h" =20 typedef struct bl_cpu_cfg { + bool cpu_is_bigendian; } BlCpuCfg; =20 void bl_gen_jump_to(const BlCpuCfg *cfg, void **p, target_ulong jump_addr); diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index ee1a1c4f20..258cc5d8c8 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -58,9 +58,9 @@ static void st_nm32_p(const BlCpuCfg *cfg, void **ptr, ui= nt32_t insn) { uint16_t *p =3D *ptr; =20 - stw_p(p, insn >> 16); + stw_endian_p(cfg->cpu_is_bigendian, p, insn >> 16); p++; - stw_p(p, insn >> 0); + stw_endian_p(cfg->cpu_is_bigendian, p, insn >> 0); p++; =20 *ptr =3D p; @@ -74,7 +74,7 @@ static void bl_gen_nop(const BlCpuCfg *cfg, void **ptr) } else { uint32_t *p =3D *ptr; =20 - stl_p(p, 0); + stl_endian_p(cfg->cpu_is_bigendian, p, 0); p++; *ptr =3D p; } @@ -95,7 +95,7 @@ static void bl_gen_r_type(const BlCpuCfg *cfg, insn =3D deposit32(insn, 6, 5, shift); insn =3D deposit32(insn, 0, 6, funct); =20 - stl_p(p, insn); + stl_endian_p(cfg->cpu_is_bigendian, p, insn); p++; =20 *ptr =3D p; @@ -113,7 +113,7 @@ static void bl_gen_i_type(const BlCpuCfg *cfg, insn =3D deposit32(insn, 16, 5, rt); insn =3D deposit32(insn, 0, 16, imm); =20 - stl_p(p, insn); + stl_endian_p(cfg->cpu_is_bigendian, p, insn); p++; =20 *ptr =3D p; diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 8e210876e1..d4dd242d0d 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -325,7 +325,7 @@ type_init(boston_register_types) =20 static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) { - const BlCpuCfg bl_cfg =3D { }; + const BlCpuCfg bl_cfg =3D { .cpu_is_bigendian =3D TARGET_BIG_ENDIAN }; uint64_t regaddr; =20 /* Move CM GCRs */ diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index a989637d3b..4fe5108845 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -165,7 +165,7 @@ static uint64_t load_kernel(MIPSCPU *cpu) static void write_bootloader(CPUMIPSState *env, uint8_t *base, uint64_t kernel_addr) { - const BlCpuCfg bl_cfg =3D { }; + const BlCpuCfg bl_cfg =3D { .cpu_is_bigendian =3D false }; uint32_t *p; =20 /* Small bootloader */ diff --git a/hw/mips/malta.c b/hw/mips/malta.c index fc485cc884..6e73c896ff 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -624,7 +624,7 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint= 64_t run_addr, static const char pci_pins_cfg[PCI_NUM_PINS] =3D { 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ }; - const BlCpuCfg bl_cfg =3D { }; + const BlCpuCfg bl_cfg =3D { .cpu_is_bigendian =3D TARGET_BIG_ENDIAN }; =20 /* Bus endianness is always reversed */ #if TARGET_BIG_ENDIAN --=20 2.45.2 From nobody Sun Nov 24 00:26:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 06/13] tests/tcg/plugins: Use the ld/st_endian_p() API Date: Mon, 30 Sep 2024 09:34:43 +0200 Message-ID: <20240930073450.33195-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philmd@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727683562372116600 Refactor to use the recently introduced ld/st_endian_p() API No logical change intended. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alex Benn=C3=A9e Reviewed-by: Pierrick Bouvier --- tests/tcg/plugins/mem.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/tests/tcg/plugins/mem.c b/tests/tcg/plugins/mem.c index b0fa8a9f27..3586d05587 100644 --- a/tests/tcg/plugins/mem.c +++ b/tests/tcg/plugins/mem.c @@ -163,13 +163,9 @@ static void update_region_info(uint64_t region, uint64= _t offset, { uint16_t *p =3D (uint16_t *) &ri->data[offset]; if (is_store) { - if (be) { - stw_be_p(p, value.data.u16); - } else { - stw_le_p(p, value.data.u16); - } + stw_endian_p(be, p, value.data.u16); } else { - uint16_t val =3D be ? lduw_be_p(p) : lduw_le_p(p); + uint16_t val =3D lduw_endian_p(be, p); unseen_data =3D val !=3D value.data.u16; } break; @@ -178,13 +174,9 @@ static void update_region_info(uint64_t region, uint64= _t offset, { uint32_t *p =3D (uint32_t *) &ri->data[offset]; if (is_store) { - if (be) { - stl_be_p(p, value.data.u32); - } else { - stl_le_p(p, value.data.u32); - } + stl_endian_p(be, p, value.data.u32); } else { - uint32_t val =3D be ? ldl_be_p(p) : ldl_le_p(p); + uint32_t val =3D ldl_endian_p(be, p); unseen_data =3D val !=3D value.data.u32; } break; @@ -193,13 +185,9 @@ static void update_region_info(uint64_t region, uint64= _t offset, { uint64_t *p =3D (uint64_t *) &ri->data[offset]; if (is_store) { - if (be) { - stq_be_p(p, value.data.u64); - } else { - stq_le_p(p, value.data.u64); - } + stq_endian_p(be, p, value.data.u64); } else { - uint64_t val =3D be ? ldq_be_p(p) : ldq_le_p(p); + uint64_t val =3D ldq_endian_p(be, p); unseen_data =3D val !=3D value.data.u64; } break; --=20 2.45.2 From nobody Sun Nov 24 00:26:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727682516; cv=none; d=zohomail.com; s=zohoarc; b=I+TdFZs9LX2BTPiQxDbg31LtVdWGU53jG2yZM6NHc6cQvl3wCqKCeIj8dIqJYYLDVrxGGfDng2RB8mDg7auT25MskInzQvOjVvAqm4vlwdxLySssigi4rJ4s6vvdHDuvFykQryWVcMuBemhPOMsmltlZxj5W+SsPYSv5xzuVdKw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727682516; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PTheN6LnDYE/7gHrhVuAVd6VlwGt/9Pb92gg++hmAlc=; b=MFsyylkjAyodujusnGieWFIZim+jDJVo5+sXTnVXGdQD68gpo8QEKYdpeLhEncFxWJ8M/lRXGDEMxUeb7dG1Rmn/J4S+c8XgzgPPvziXSVLsdB/UY1ueNwj3prj+JQL0b5qGrnqTZIEyD+zMya2BCv9xtILuWq5U7gN2b459KEI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727682516302345.4077173340029; Mon, 30 Sep 2024 00:48:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svAzc-0004Dy-OC; Mon, 30 Sep 2024 03:38:54 -0400 Received: from eggs.gnu.org ([209.51.188.92]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svAz9-00043M-Qr for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:38:25 -0400 Received: from [2a00:1450:4864:20::32e] (helo=mail-wm1-x32e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svAyA-00008z-99 for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:38:10 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-42cb1758e41so29051145e9.1 for ; Mon, 30 Sep 2024 00:36:08 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 07/13] hw/xtensa/xtfpga: Remove TARGET_BIG_ENDIAN #ifdef'ry Date: Mon, 30 Sep 2024 09:34:44 +0200 Message-ID: <20240930073450.33195-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32e (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RDNS_NONE=0.793, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727682517902116600 Move code evaluation from preprocessor to compiler so both if() ladders are processed. Mostly style change. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Thomas Huth --- hw/xtensa/xtfpga.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 955e8867a3..228f00b045 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -415,8 +415,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, M= achineState *machine) } } if (entry_point !=3D env->pc) { - uint8_t boot[] =3D { -#if TARGET_BIG_ENDIAN + uint8_t boot_be[] =3D { 0x60, 0x00, 0x08, /* j 1f */ 0x00, /* .literal_position */ 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ @@ -425,7 +424,8 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, M= achineState *machine) 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ 0x0a, 0x00, 0x00, /* jx a0 */ -#else + }; + uint8_t boot_le[] =3D { 0x06, 0x02, 0x00, /* j 1f */ 0x00, /* .literal_position */ 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ @@ -434,14 +434,16 @@ static void xtfpga_init(const XtfpgaBoardDesc *board,= MachineState *machine) 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ 0xa0, 0x00, 0x00, /* jx a0 */ -#endif }; + const size_t boot_sz =3D TARGET_BIG_ENDIAN ? sizeof(boot_be) + : sizeof(boot_le); + uint8_t *boot =3D TARGET_BIG_ENDIAN ? boot_be : boot_le; uint32_t entry_pc =3D tswap32(entry_point); uint32_t entry_a2 =3D tswap32(tagptr); =20 memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); - cpu_physical_memory_write(env->pc, boot, sizeof(boot)); + cpu_physical_memory_write(env->pc, boot, boot_sz); } } else { if (flash) { --=20 2.45.2 From nobody Sun Nov 24 00:26:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727685917; cv=none; d=zohomail.com; s=zohoarc; b=FI5mt+jxuKIlxOwMy05fCuE194PuqBYm4bBFCgT8MohDQrlIj/pJScz5FexcnZMYOsK5rOAOqG7IEjGBuaI9TxLaCcyNpcyCVGND9W6i4EEwThYW9GnPaWoj8LOirlXmxdcgRTAHlYq8UBaW/UOFsgbBdwV4DdyebjMNANsbGkI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727685917; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Zn1QOBKpxwHC7pwp1nDkwIemv7qUJthxbF0WBocU5ZE=; b=OXMzQE5GwjEASRO6z7BEYz2uCWaMwkgW3eADFxjYPVIIKiwV7m0kU0QKGVR9pswFRBS9gwQ6CSn6kNFnASoPK5JaumA/kuO20y/ON6nZ/2oj/ITf4XvfdiroZV+MGNY8B/3pcPMzfieMy9ekrBnJxQ44LRM+iPnTn60qvKCGNl8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727685917213672.018803617795; Mon, 30 Sep 2024 01:45:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svAzl-0004Ra-Oe; Mon, 30 Sep 2024 03:39:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svAzG-0004Av-8J for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:38:32 -0400 Received: from [2a00:1450:4864:20::436] (helo=mail-wr1-x436.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svAyV-00009T-5d for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:38:19 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-37cdac05af9so2062353f8f.0 for ; Mon, 30 Sep 2024 00:36:10 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 08/13] hw/xtensa/xtfpga: Replace memcpy()+tswap32() by stl_endian_p() Date: Mon, 30 Sep 2024 09:34:45 +0200 Message-ID: <20240930073450.33195-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::436 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727685918792116600 Replace a pair of memcpy() + tswap32() by stl_endian_p(), which also swap the value using target endianness. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- hw/xtensa/xtfpga.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 228f00b045..521fe84b01 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -438,11 +438,9 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, = MachineState *machine) const size_t boot_sz =3D TARGET_BIG_ENDIAN ? sizeof(boot_be) : sizeof(boot_le); uint8_t *boot =3D TARGET_BIG_ENDIAN ? boot_be : boot_le; - uint32_t entry_pc =3D tswap32(entry_point); - uint32_t entry_a2 =3D tswap32(tagptr); =20 - memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); - memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); + stl_endian_p(TARGET_BIG_ENDIAN, boot + 4, entry_point); + stl_endian_p(TARGET_BIG_ENDIAN, boot + 8, tagptr); cpu_physical_memory_write(env->pc, boot, boot_sz); } } else { --=20 2.45.2 From nobody Sun Nov 24 00:26:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727683621; cv=none; d=zohomail.com; s=zohoarc; b=nIVZIJrqd9zReIK5xE4E9Kn7S49KZCCEtIrgjyBhN6jf7QeNkqc2Mu73UpuDt192BIwbHK1hEB5hyw741mRDt6GRMg4yfT3yz9IG8/WmmSqPUTgXCcOAr7AqfHiHSovr0hLBtz1I4QuTcBLCELOlMwCE2FVjAIorA3BjO2EkXk4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727683621; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RyfJ60ZwiZ7J7acEGIws/WvnHoIJtgQD50MT+DOE6Vo=; b=J7l8yl+F6dlMBuxVCKtm17+YdBRFEeRdW5bHV1ag3becyI/a5yruMWuE+7yiIwkps8kk0/E60z8yaqta6JbHcCinlw47KH4ndr0QgDDC9yh7r6F0u4yl9c2YwF64uDeVw+rC8s6d+DoWsb0g+gvbiLcyNcJCJ4hCEAbthmD48PM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727683621849588.6869635522795; Mon, 30 Sep 2024 01:07:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svBQW-0000Yt-Gy; Mon, 30 Sep 2024 04:06:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svBQS-0000Kk-Sy for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:06:37 -0400 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svBQR-0004Wi-6R for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:06:36 -0400 Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-5c42e7adbddso5870466a12.2 for ; Mon, 30 Sep 2024 01:06:34 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 09/13] exec/memory_ldst_phys: Introduce ld/st_endian_phys() API Date: Mon, 30 Sep 2024 09:34:46 +0200 Message-ID: <20240930073450.33195-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=philmd@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727683622081116600 Introduce the ld/st_endian_phys() API, which takes an extra boolean argument to dispatch to ld/st_{be,le}_phys() methods. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- TODO: Update docstring regexp --- include/exec/memory_ldst_phys.h.inc | 66 +++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/include/exec/memory_ldst_phys.h.inc b/include/exec/memory_ldst= _phys.h.inc index ecd678610d..8ea162b40d 100644 --- a/include/exec/memory_ldst_phys.h.inc +++ b/include/exec/memory_ldst_phys.h.inc @@ -74,6 +74,16 @@ static inline uint16_t glue(lduw_be_phys, SUFFIX)(ARG1_D= ECL, hwaddr addr) MEMTXATTRS_UNSPECIFIED, NUL= L); } =20 +static inline uint16_t glue(lduw_endian_phys, SUFFIX)(bool big_endian, + ARG1_DECL, hwaddr ad= dr) +{ + return big_endian + ? glue(address_space_lduw_le, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, N= ULL) + : glue(address_space_lduw_be, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, N= ULL); +} + static inline uint32_t glue(ldl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr) { return glue(address_space_ldl_le, SUFFIX)(ARG1, addr, @@ -86,6 +96,16 @@ static inline uint32_t glue(ldl_be_phys, SUFFIX)(ARG1_DE= CL, hwaddr addr) MEMTXATTRS_UNSPECIFIED, NULL= ); } =20 +static inline uint32_t glue(ldl_endian_phys, SUFFIX)(bool big_endian, + ARG1_DECL, hwaddr add= r) +{ + return big_endian + ? glue(address_space_ldl_le, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NU= LL) + : glue(address_space_ldl_be, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NU= LL); +} + static inline uint64_t glue(ldq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr) { return glue(address_space_ldq_le, SUFFIX)(ARG1, addr, @@ -98,6 +118,16 @@ static inline uint64_t glue(ldq_be_phys, SUFFIX)(ARG1_D= ECL, hwaddr addr) MEMTXATTRS_UNSPECIFIED, NULL= ); } =20 +static inline uint32_t glue(ldq_endian_phys, SUFFIX)(bool big_endian, + ARG1_DECL, hwaddr add= r) +{ + return big_endian + ? glue(address_space_ldq_le, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NU= LL) + : glue(address_space_ldq_be, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NU= LL); +} + static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint8_t = val) { glue(address_space_stb, SUFFIX)(ARG1, addr, val, @@ -116,6 +146,18 @@ static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL= , hwaddr addr, uint16_t va MEMTXATTRS_UNSPECIFIED, NULL); } =20 +static inline void glue(stw_endian_phys, SUFFIX)(bool big_endian, ARG1_DEC= L, + hwaddr addr, uint16_t val) +{ + if (big_endian) { + glue(address_space_stw_be, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } else { + glue(address_space_stw_le, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } +} + static inline void glue(stl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint3= 2_t val) { glue(address_space_stl_le, SUFFIX)(ARG1, addr, val, @@ -128,6 +170,18 @@ static inline void glue(stl_be_phys, SUFFIX)(ARG1_DECL= , hwaddr addr, uint32_t va MEMTXATTRS_UNSPECIFIED, NULL); } =20 +static inline void glue(stl_endian_phys, SUFFIX)(bool big_endian, ARG1_DEC= L, + hwaddr addr, uint32_t val) +{ + if (big_endian) { + glue(address_space_stl_be, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } else { + glue(address_space_stl_le, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } +} + static inline void glue(stq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint6= 4_t val) { glue(address_space_stq_le, SUFFIX)(ARG1, addr, val, @@ -139,6 +193,18 @@ static inline void glue(stq_be_phys, SUFFIX)(ARG1_DECL= , hwaddr addr, uint64_t va glue(address_space_stq_be, SUFFIX)(ARG1, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } + +static inline void glue(stq_endian_phys, SUFFIX)(bool big_endian, ARG1_DEC= L, + hwaddr addr, uint64_t val) +{ + if (big_endian) { + glue(address_space_stq_be, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } else { + glue(address_space_stq_le, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } +} #endif =20 #undef ARG1_DECL --=20 2.45.2 From nobody Sun Nov 24 00:26:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727683507; cv=none; d=zohomail.com; s=zohoarc; b=REAYQ8NIxZLCee15jU/lJ092/L63vi7zRiiFyJNMOOvN0svPNAyvk8bcKyk4Ksmogc8KyKONv85L3DyuqaqAP2lhMKtPt9luXDu9xaY6NGObYQpI9zxezn+a6CsNzqpYXDCxmyyXHZzp8Gl6v84bJuuuBVs7lfO7lLyeyor39kM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 10/13] hw/virtio/virtio-access: Use ld/st_endian_phys() API Date: Mon, 30 Sep 2024 09:34:47 +0200 Message-ID: <20240930073450.33195-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=philmd@linaro.org; helo=mail-lj1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727683508711116600 Refactor to use the recently introduced ld/st_endian_phys() API. No logical change intended. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/hw/virtio/virtio-access.h | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) diff --git a/include/hw/virtio/virtio-access.h b/include/hw/virtio/virtio-a= ccess.h index b920874be8..37a42407ea 100644 --- a/include/hw/virtio/virtio-access.h +++ b/include/hw/virtio/virtio-access.h @@ -43,30 +43,21 @@ static inline uint16_t virtio_lduw_phys(VirtIODevice *v= dev, hwaddr pa) { AddressSpace *dma_as =3D vdev->dma_as; =20 - if (virtio_access_is_big_endian(vdev)) { - return lduw_be_phys(dma_as, pa); - } - return lduw_le_phys(dma_as, pa); + return lduw_endian_phys(virtio_access_is_big_endian(vdev), dma_as, pa); } =20 static inline uint32_t virtio_ldl_phys(VirtIODevice *vdev, hwaddr pa) { AddressSpace *dma_as =3D vdev->dma_as; =20 - if (virtio_access_is_big_endian(vdev)) { - return ldl_be_phys(dma_as, pa); - } - return ldl_le_phys(dma_as, pa); + return ldl_endian_phys(virtio_access_is_big_endian(vdev), dma_as, pa); } =20 static inline uint64_t virtio_ldq_phys(VirtIODevice *vdev, hwaddr pa) { AddressSpace *dma_as =3D vdev->dma_as; =20 - if (virtio_access_is_big_endian(vdev)) { - return ldq_be_phys(dma_as, pa); - } - return ldq_le_phys(dma_as, pa); + return ldq_endian_phys(virtio_access_is_big_endian(vdev), dma_as, pa); } =20 static inline void virtio_stw_phys(VirtIODevice *vdev, hwaddr pa, @@ -74,11 +65,7 @@ static inline void virtio_stw_phys(VirtIODevice *vdev, h= waddr pa, { AddressSpace *dma_as =3D vdev->dma_as; =20 - if (virtio_access_is_big_endian(vdev)) { - stw_be_phys(dma_as, pa, value); - } else { - stw_le_phys(dma_as, pa, value); - } + stw_endian_phys(virtio_access_is_big_endian(vdev), dma_as, pa, value); } =20 static inline void virtio_stl_phys(VirtIODevice *vdev, hwaddr pa, @@ -86,11 +73,7 @@ static inline void virtio_stl_phys(VirtIODevice *vdev, h= waddr pa, { AddressSpace *dma_as =3D vdev->dma_as; =20 - if (virtio_access_is_big_endian(vdev)) { - stl_be_phys(dma_as, pa, value); - } else { - stl_le_phys(dma_as, pa, value); - } + stl_endian_phys(virtio_access_is_big_endian(vdev), dma_as, pa, value); } =20 static inline void virtio_stw_p(VirtIODevice *vdev, void *ptr, uint16_t v) --=20 2.45.2 From nobody Sun Nov 24 00:26:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727683745; cv=none; d=zohomail.com; s=zohoarc; b=J3E1sBucu7XXVqaYfgRk8IdSrnCtWX01Lm4eTVgdku3DiS5qUYXPxbZWwUlvR+GjiZix1Z9gl7eRuBAixzDQp7xzGUrDr73yprRvizpEVfgCd0k10TRa+iLNi2mb1wKaDtjRoo+Wtxl4PhdFpHT4OmtMx3UWhABVIupfI2MmA4I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727683745; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=olm5MEqTuo7Wlc02c6b6qRoX+TEZG1pRsM1M0qwZSUk=; b=hiN1GnTzvjj/4pBB5w4L5b0jxH8zuEfmfwIrR+LP9XORLn8Q8V6DlLQIjgwa2RX46DhQ7WeDCxKhp1fw0xuhyVy5N5TTWcRLx4qE4g3+AOm7wqWtaYrgQO5q2V7S18ZigEh5NhFDuIPQOnjboVsVPeFFt474rbSZ+RAASGjpTSM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727683745264981.2581394968072; Mon, 30 Sep 2024 01:09:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svBSE-000852-Og; Mon, 30 Sep 2024 04:08:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svBS7-0007jd-Qy for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:08:22 -0400 Received: from mail-lf1-x136.google.com ([2a00:1450:4864:20::136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svBS6-0004gM-3p for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:08:19 -0400 Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-539983beb19so260803e87.3 for ; Mon, 30 Sep 2024 01:08:17 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 11/13] hw/pci/pci_device: Add PCI_DMA_DEFINE_LDST_END() macro Date: Mon, 30 Sep 2024 09:34:48 +0200 Message-ID: <20240930073450.33195-12-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=philmd@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727683746637116600 Define both endianness variants with a single macro. Useful to add yet other endian specific definitions in the next commit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/hw/pci/pci_device.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index 91df40f989..ff619241a4 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -298,13 +298,14 @@ static inline MemTxResult pci_dma_write(PCIDevice *de= v, dma_addr_t addr, return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs);= \ } =20 +#define PCI_DMA_DEFINE_LDST_END(_l, _s, _bits) \ + PCI_DMA_DEFINE_LDST(_l##_le, _s##_le, _bits) \ + PCI_DMA_DEFINE_LDST(_l##_be, _s##_be, _bits) + PCI_DMA_DEFINE_LDST(ub, b, 8); -PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) -PCI_DMA_DEFINE_LDST(l_le, l_le, 32); -PCI_DMA_DEFINE_LDST(q_le, q_le, 64); -PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) -PCI_DMA_DEFINE_LDST(l_be, l_be, 32); -PCI_DMA_DEFINE_LDST(q_be, q_be, 64); +PCI_DMA_DEFINE_LDST_END(uw, w, 16) +PCI_DMA_DEFINE_LDST_END(l, l, 32) +PCI_DMA_DEFINE_LDST_END(q, q, 64) =20 #undef PCI_DMA_DEFINE_LDST =20 --=20 2.45.2 From nobody Sun Nov 24 00:26:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727682516; cv=none; d=zohomail.com; s=zohoarc; b=eLP8FfyG+m42HEM1PjGZdb8lmSu4pjoUUHLD7riyt0P46CCiJBvCcGHEj7+Oo6gu7im+VCxfqJ9rDbSVVwZ/vt3gIvT/3/RTkaRkzDYmcetSl4NewZDgrOrCRqAenwP1UM3dpbcpuhVYoBJnI6MwPIhQTALWw0zNRGQ9gI/Z1MA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727682516; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=J3QK0sGMtG8TI1HL5/V5FwLZQoUZnlZNYr8FgmUN/RY=; b=fGqgdzVTU0tJhG0PA8GT7Oy/Ri5noKXkUso834gA8SbO/QRrEm1y2Fz9tm+ADKtcRZB15zaj9vphNVxCazmW0Jp22xBvDhcw3rnJV79m0ybIWwZ4+kLOqh1/O/n/sfMqfluUzfPla6WVMGX9psS7cOugzxLPXC6HB2AJlnSsm9o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727682516803710.7986057161518; Mon, 30 Sep 2024 00:48:36 -0700 (PDT) Received: from [::1] (helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svB5i-0006no-VS; Mon, 30 Sep 2024 03:45:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svB58-0006ha-DP for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:44:52 -0400 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svB4D-0000X2-Au for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:44:20 -0400 Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-5c87c7d6ad4so3757393a12.3 for ; Mon, 30 Sep 2024 00:42:45 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 12/13] hw/pci/pci_device: Introduce ld/st_endian_pci_dma() API Date: Mon, 30 Sep 2024 09:34:49 +0200 Message-ID: <20240930073450.33195-13-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=philmd@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727682517677116600 Introduce the ld/st_endian_pci_dma() API, which takes an extra boolean argument to dispatch to ld/st_{be,le}_pci_dma() methods. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- TODO: Update docstring regexp --- include/hw/pci/pci_device.h | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index ff619241a4..dc9b17dded 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -300,7 +300,29 @@ static inline MemTxResult pci_dma_write(PCIDevice *dev= , dma_addr_t addr, =20 #define PCI_DMA_DEFINE_LDST_END(_l, _s, _bits) \ PCI_DMA_DEFINE_LDST(_l##_le, _s##_le, _bits) \ - PCI_DMA_DEFINE_LDST(_l##_be, _s##_be, _bits) + PCI_DMA_DEFINE_LDST(_l##_be, _s##_be, _bits) \ + static inline MemTxResult ld##_l##_endian_pci_dma(bool is_big_endian, \ + PCIDevice *dev, \ + dma_addr_t addr, \ + uint##_bits##_t *val= , \ + MemTxAttrs attrs) \ + { \ + AddressSpace *pci_as =3D pci_get_address_space(dev); \ + return is_big_endian \ + ? ld##_l##_be_dma(pci_as, addr, val, attrs) \ + : ld##_l##_le_dma(pci_as, addr, val, attrs); \ + } \ + static inline MemTxResult st##_s##_endian_pci_dma(bool is_big_endian, \ + PCIDevice *dev, \ + dma_addr_t addr, \ + uint##_bits##_t val,= \ + MemTxAttrs attrs) \ + { \ + AddressSpace *pci_as =3D pci_get_address_space(dev); \ + return is_big_endian \ + ? st##_s##_be_dma(pci_as, addr, val, attrs) \ + : st##_s##_le_dma(pci_as, addr, val, attrs); \ + } =20 PCI_DMA_DEFINE_LDST(ub, b, 8); PCI_DMA_DEFINE_LDST_END(uw, w, 16) --=20 2.45.2 From nobody Sun Nov 24 00:26:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1727683329; cv=none; d=zohomail.com; s=zohoarc; b=FWpcSDYrilGANGlkI1vF2SZA07dVCdWva02OJEyeb3jqkVtkBLzI71z6K01NxdaDa0Kb7axv9wuZRzrxn+sdQ83XJH+1xSUl5IzLio2Bn9PgqgBdoXyerC5m79+sHc8FqgxCxSdC6lkdyEuSQFg7Xx4FW3wq+ljJcLIshbnicu0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727683329; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qgFNx5loGg07bkVRCAPUaZ+t66SDahiEcwbYBeR9pKk=; b=UzBrui72TVSKlZfChvXfyIcrY5nXxVujYT2B8kFcMT1AK6qBY8Jfu2vfsicExVLgWWrlghncg/r1h0SGNaZK5tfWiMycuQ6sTd8KFxVNlws/EaxQb5Cz95w4ADY6cLivgbpk1wOexVAJ2BBQv84yjk0Mm6kIC0k8kT7LeG+FMJY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727683329384787.3508677710287; Mon, 30 Sep 2024 01:02:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svBLf-0006Y7-2D; Mon, 30 Sep 2024 04:01:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svBLO-0006A2-U0 for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:01:33 -0400 Received: from mail-lf1-x136.google.com ([2a00:1450:4864:20::136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svBLN-0003i2-AH for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:01:22 -0400 Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-5398e53ca28so1296609e87.3 for ; Mon, 30 Sep 2024 01:01:20 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 13/13] hw/net/tulip: Use ld/st_endian_pci_dma() API Date: Mon, 30 Sep 2024 09:34:50 +0200 Message-ID: <20240930073450.33195-14-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=philmd@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1727683331573116600 Refactor to use the recently introduced ld/st_endian_pci_dma() API. No logical change intended. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- hw/net/tulip.c | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/hw/net/tulip.c b/hw/net/tulip.c index 9df3e17162..6c67958da7 100644 --- a/hw/net/tulip.c +++ b/hw/net/tulip.c @@ -71,36 +71,24 @@ static void tulip_desc_read(TULIPState *s, hwaddr p, struct tulip_descriptor *desc) { const MemTxAttrs attrs =3D { .memory =3D true }; + bool use_big_endian =3D s->csr[0] & CSR0_DBO; =20 - if (s->csr[0] & CSR0_DBO) { - ldl_be_pci_dma(&s->dev, p, &desc->status, attrs); - ldl_be_pci_dma(&s->dev, p + 4, &desc->control, attrs); - ldl_be_pci_dma(&s->dev, p + 8, &desc->buf_addr1, attrs); - ldl_be_pci_dma(&s->dev, p + 12, &desc->buf_addr2, attrs); - } else { - ldl_le_pci_dma(&s->dev, p, &desc->status, attrs); - ldl_le_pci_dma(&s->dev, p + 4, &desc->control, attrs); - ldl_le_pci_dma(&s->dev, p + 8, &desc->buf_addr1, attrs); - ldl_le_pci_dma(&s->dev, p + 12, &desc->buf_addr2, attrs); - } + ldl_endian_pci_dma(use_big_endian, &s->dev, p, &desc->status, attrs); + ldl_endian_pci_dma(use_big_endian, &s->dev, p + 4, &desc->control, att= rs); + ldl_endian_pci_dma(use_big_endian, &s->dev, p + 8, &desc->buf_addr1, a= ttrs); + ldl_endian_pci_dma(use_big_endian, &s->dev, p + 12, &desc->buf_addr2, = attrs); } =20 static void tulip_desc_write(TULIPState *s, hwaddr p, struct tulip_descriptor *desc) { const MemTxAttrs attrs =3D { .memory =3D true }; + bool use_big_endian =3D s->csr[0] & CSR0_DBO; =20 - if (s->csr[0] & CSR0_DBO) { - stl_be_pci_dma(&s->dev, p, desc->status, attrs); - stl_be_pci_dma(&s->dev, p + 4, desc->control, attrs); - stl_be_pci_dma(&s->dev, p + 8, desc->buf_addr1, attrs); - stl_be_pci_dma(&s->dev, p + 12, desc->buf_addr2, attrs); - } else { - stl_le_pci_dma(&s->dev, p, desc->status, attrs); - stl_le_pci_dma(&s->dev, p + 4, desc->control, attrs); - stl_le_pci_dma(&s->dev, p + 8, desc->buf_addr1, attrs); - stl_le_pci_dma(&s->dev, p + 12, desc->buf_addr2, attrs); - } + stl_endian_pci_dma(use_big_endian, &s->dev, p, desc->status, attrs); + stl_endian_pci_dma(use_big_endian, &s->dev, p + 4, desc->control, attr= s); + stl_endian_pci_dma(use_big_endian, &s->dev, p + 8, desc->buf_addr1, at= trs); + stl_endian_pci_dma(use_big_endian, &s->dev, p + 12, desc->buf_addr2, a= ttrs); } =20 static void tulip_update_int(TULIPState *s) --=20 2.45.2