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Sat, 28 Sep 2024 03:04:59 -0700 (PDT) From: phil@philjordan.eu To: qemu-devel@nongnu.org Cc: dirty@apple.com, rbolshakov@ddn.com, lists@philjordan.eu, philmd@linaro.org, minhquangbui99@gmail.com, akihiko.odaki@daynix.com, Phil Dennis-Jordan Subject: [PATCH v2] i386/hvf: Integrates x2APIC support with hvf accel Date: Sat, 28 Sep 2024 12:04:50 +0200 Message-Id: <20240928100450.1666-1-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-146) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: neutral client-ip=2a00:1450:4864:20::32e; envelope-from=phil@philjordan.eu; helo=mail-wm1-x32e.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @philjordan-eu.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1727517959478116600 From: Phil Dennis-Jordan Support for x2APIC mode was recently introduced in the software emulated APIC implementation for TCG. Enabling it when using macOS=E2=80=99s hvf accelerator is useful and significantly helps performance, as Qemu currently uses the emulated APIC when running on hvf as well. This change wires up the read & write operations for the MSR VM exits and allow-lists the CPUID flag in the x86 hvf runtime. Signed-off-by: Phil Dennis-Jordan Acked-by: Bui Quang Minh --- v2: * Rebased on latest upstream post v9.1 release * Minor cleanup in x2APIC MSR index calculation target/i386/hvf/x86_cpuid.c | 4 ++-- target/i386/hvf/x86_emu.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c index e56cd8411b..4f260d46a8 100644 --- a/target/i386/hvf/x86_cpuid.c +++ b/target/i386/hvf/x86_cpuid.c @@ -64,8 +64,8 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t = idx, CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS; ecx &=3D CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | - CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | - CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_MOVBE | + CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_S= SE41 | + CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | CPUID_EXT_POPCNT | CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND; ecx |=3D CPUID_EXT_HYPERVISOR; diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 38c782b8e3..f90c79e083 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -663,6 +663,15 @@ static void exec_lods(CPUX86State *env, struct x86_dec= ode *decode) env->eip +=3D decode->len; } =20 +static void raise_exception(CPUX86State *env, int exception_index, + int error_code) +{ + env->exception_nr =3D exception_index; + env->error_code =3D error_code; + env->has_error_code =3D true; + env->exception_injected =3D 1; +} + void simulate_rdmsr(CPUX86State *env) { X86CPU *cpu =3D env_archcpu(env); @@ -677,6 +686,16 @@ void simulate_rdmsr(CPUX86State *env) case MSR_IA32_APICBASE: val =3D cpu_get_apic_base(cpu->apic_state); break; + case MSR_APIC_START ... MSR_APIC_END: { + int ret; + int index =3D msr - MSR_APIC_START; + + ret =3D apic_msr_read(index, &val); + if (ret < 0) { + raise_exception(env, EXCP0D_GPF, 0); + } + break; + } case MSR_IA32_UCODE_REV: val =3D cpu->ucode_rev; break; @@ -777,6 +796,16 @@ void simulate_wrmsr(CPUX86State *env) case MSR_IA32_APICBASE: cpu_set_apic_base(cpu->apic_state, data); break; + case MSR_APIC_START ... MSR_APIC_END: { + int ret; + int index =3D msr - MSR_APIC_START; + + ret =3D apic_msr_write(index, data); + if (ret < 0) { + raise_exception(env, EXCP0D_GPF, 0); + } + break; + } case MSR_FSBASE: wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data); break; --=20 2.39.3 (Apple Git-146)