From nobody Sun Nov 24 03:58:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1727426183; cv=none; d=zohomail.com; s=zohoarc; b=D0alOLiKQv66k1efZ0J/CNxcIiVFfxH8HOyiVz6848a06R6We1yFpCPXFzl1QRrhBfXYGfe1+8ahuZMA8eN/AleNpxWDxtpjZUIBotguEF0PrvEyZbchHLUwOg7M0GMuN+kStLvPkcBlZcc5kIk2zVJ8Hs4IOn1BAbN2W6ORxps= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1727426183; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Cuelhesp2EJkf6+kUOINt1uwensPR6dAhjz7egcQUKc=; b=VTpCHv8sMH/+FSMSXwa8v6Sltl5Jh5X7buDHXMy3uCXPAPQsJ4EoPPPOtmNDCtazPABQ5rpr/s1HSlFCRexuT17maXARG4Wifd2kwqPwJRwUAXXHR6xYU3ab5C+jVotNe0jOGisxW/0R8DTvtxz4tTm4GMQpgEMUrtl9Y8Xq+es= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1727426183523818.5871869004739; Fri, 27 Sep 2024 01:36:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1su6Qt-0007Qg-Tx; Fri, 27 Sep 2024 04:34:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1su6QZ-00076b-Ea; Fri, 27 Sep 2024 04:34:18 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1su6QV-0003ff-Jm; Fri, 27 Sep 2024 04:34:14 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 27 Sep 2024 16:33:52 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 27 Sep 2024 16:33:52 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Thomas Huth , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v5 4/7] hw/gpio/aspeed: Fix clear incorrect interrupt status for GPIO index mode Date: Fri, 27 Sep 2024 16:33:48 +0800 Message-ID: <20240927083351.2637798-5-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240927083351.2637798-1-jamin_lin@aspeedtech.com> References: <20240927083351.2637798-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1727426185639116600 Content-Type: text/plain; charset="utf-8" The interrupt status field is W1C, where a set bit on read indicates an interrupt is pending. If the bit extracted from data is set it should clear the corresponding bit in reg_value. However, if the extracted bit is clear then the value of the corresponding bit in reg_value should be unchanged. SHARED_FIELD_EX32() extracts the interrupt status bit from the write (data). reg_value is set to the set's interrupt status, which means that for any pin with an interrupt pending, the corresponding bit is set. The deposit32() call updates the bit at pin_idx in the reg_value, using the value extracted from the write (data). The result is that if multiple interrupt status bits were pending and the write was acknowledging specific one bit, then the all interrupt status bits will be cleared. However, it is index mode and should only clear the corresponding bit. For example, say we have an interrupt pending for GPIOA0, where the following statements are true: set->int_status =3D=3D 0b01 s->pending =3D=3D 1 Before it is acknowledged, an interrupt becomes pending for GPIOA1: set->int_status =3D=3D 0b11 s->pending =3D=3D 2 A write is issued to acknowledge the interrupt for GPIOA0. This causes the following sequence: reg_value =3D=3D 0b11 pending =3D=3D 2 s->pending =3D=3D 0 set->int_status =3D=3D 0b00 It should only clear bit 0 in index mode and the correct result should be as following. set->int_status =3D=3D 0b11 s->pending =3D=3D 2 pending =3D=3D 1 s->pending =3D=3D 1 set->int_status =3D=3D 0b10 Signed-off-by: Jamin Lin Suggested-by: Andrew Jeffery Reviewed-by: Andrew Jeffery --- hw/gpio/aspeed_gpio.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index 8725606aec..16c18ea2f7 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -641,7 +641,7 @@ static void aspeed_gpio_write_index_mode(void *opaque, = hwaddr offset, uint32_t pin_idx =3D reg_idx_number % ASPEED_GPIOS_PER_SET; uint32_t group_idx =3D pin_idx / GPIOS_PER_GROUP; uint32_t reg_value =3D 0; - uint32_t cleared; + uint32_t pending =3D 0; =20 set =3D &s->sets[set_idx]; props =3D &agc->props[set_idx]; @@ -703,16 +703,23 @@ static void aspeed_gpio_write_index_mode(void *opaque= , hwaddr offset, FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_2)= ); set->int_sens_2 =3D update_value_control_source(set, set->int_sens= _2, reg_value); - /* set interrupt status */ - reg_value =3D set->int_status; - reg_value =3D deposit32(reg_value, pin_idx, 1, - FIELD_EX32(data, GPIO_INDEX_REG, INT_STATUS)= ); - cleared =3D ctpop32(reg_value & set->int_status); - if (s->pending && cleared) { - assert(s->pending >=3D cleared); - s->pending -=3D cleared; + /* interrupt status */ + if (FIELD_EX32(data, GPIO_INDEX_REG, INT_STATUS)) { + /* pending is either 1 or 0 for a 1-bit field */ + pending =3D extract32(set->int_status, pin_idx, 1); + + assert(s->pending >=3D pending); + + /* No change to s->pending if pending is 0 */ + s->pending -=3D pending; + + /* + * The write acknowledged the interrupt regardless of whether = it + * was pending or not. The post-condition is that it mustn't be + * pending. Unconditionally clear the status bit. + */ + set->int_status =3D deposit32(set->int_status, pin_idx, 1, 0); } - set->int_status &=3D ~reg_value; break; case gpio_reg_idx_debounce: reg_value =3D set->debounce_1; --=20 2.34.1