From nobody Wed Oct 23 00:35:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1726725368; cv=none; d=zohomail.com; s=zohoarc; b=LlQDkqzPbtQT0Kf5b2Dr9XSI2/vqOGlDjmP2eImEnFhlz02yo7kPNCgzPqm80UgFLwmNmeLb3KB3z5Jegi2NX/CDPfjupqA1rVmX7I0vo6bduZLH2om9w8Wk0tclUXo24W6pQKMtLaZKNffCAlJK84/4lU7CtzebJxHP8eMY7pU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726725368; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OYoWwuTCjnhZKVW1fPb6oXyFhZWVqQr9eyJZjOgXeqU=; b=V09U7ljyw1tR/n+6vrl8h3S96fot5gUohWcj3wSGLXcZKDqmYYPcY5F9t/Jn8fJ8x5r5T+UCv/W9dVj/NtU/PeSeqHxu76WnujJPi6RoZgmjNRKVzekC1vfP+sQHGEdW+1B/eEvZ54KdcHwuAnbhKTjNxxYmSqOzSnBW7BpAjS8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726725368614675.3824175056094; Wed, 18 Sep 2024 22:56:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1srA8s-0004vp-15; Thu, 19 Sep 2024 01:55:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1srA8p-0004jh-Lt; Thu, 19 Sep 2024 01:55:47 -0400 Received: from out30-119.freemail.mail.aliyun.com ([115.124.30.119]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1srA8l-0007KL-Pr; Thu, 19 Sep 2024 01:55:46 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0WFGZSGM_1726725335) by smtp.aliyun-inc.com; Thu, 19 Sep 2024 13:55:36 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1726725337; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=OYoWwuTCjnhZKVW1fPb6oXyFhZWVqQr9eyJZjOgXeqU=; b=NlDipZ36wqsNimCsSzAuYGusrowk9fgKcjCtRYBjS10Nq2ecEeNNhWNbJ6jf40zLPAjkGBLqdqjVDj82nT8mehghnIeZxSLmF7Yffn4Nt2RrBkJe7f593xDmH9iMAGJgwHK+bQ76+NMNupwaz8zVsi0mfEH0Uj0X/APL/eilAUw= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com Subject: [PATCH v7 7/8] target/riscv: Add max32 CPU for RV64 QEMU Date: Thu, 19 Sep 2024 13:50:47 +0800 Message-Id: <20240919055048.562-8-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240919055048.562-1-zhiwei_liu@linux.alibaba.com> References: <20240919055048.562-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.119; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-119.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1726725369780116600 Content-Type: text/plain; charset="utf-8" We may need 32-bit max for RV64 QEMU. Thus we add these two CPUs for RV64 QEMU. The reason we don't expose them to RV32 QEMU is that we already have max cpu with the same configuration. Another reason is that we want to follow the RISC-V custom where addw instruction doesn't exist in RV32 CPU. Signed-off-by: LIU Zhiwei Suggested-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 12 +++++++----- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 4464c0fd7a..62115375cd 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -30,6 +30,7 @@ #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) =20 #define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max") +#define TYPE_RISCV_CPU_MAX32 RISCV_CPU_TYPE_NAME("max32") #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 86ce15252a..baf8fba467 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -448,11 +448,9 @@ static void riscv_max_cpu_init(Object *obj) =20 env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY -#ifdef TARGET_RISCV32 - set_satp_mode_max_supported(cpu, VM_1_10_SV32); -#else - set_satp_mode_max_supported(cpu, VM_1_10_SV57); -#endif + set_satp_mode_max_supported(RISCV_CPU(obj), + riscv_cpu_mxl(&RISCV_CPU(obj)->env) =3D=3D MXL_RV32 ? + VM_1_10_SV32 : VM_1_10_SV57); #endif } =20 @@ -2945,6 +2943,10 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu= _init), #endif =20 +#if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX32, MXL_RV32, riscv_max_cpu_= init), +#endif + #if defined(TARGET_RISCV64) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_= init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_= cpu_init), --=20 2.43.0