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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2dd608e2318sm1914577a91.32.2024.09.18.10.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2024 10:14:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1726679694; x=1727284494; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f408neNmJiHRMFNBITqjdfGcu6sd/hAmiLVrUqm2xBk=; b=ZHUYgjXDcDxRq2RdAX2ki5uX15Vgl0RZNgHH57zghRvRfUcRvze05mVuLHz2cmpi7J PvNDs9R/6xSzcvd8wbHqF8AQR2Vpq9MsAGYfeOOrIJVZrdKdo8mmU1500RklL4/ZNs4E xmc5pFn4vNrwX4pOdydljN6uo+bwWsaJgG/tyElyQJHFtCR80G/xK/Acp8ArVC048MEi FHIBQ+0DbXE6fE0IpPrVUwiDLd/pTanld+uAIl6xslaNaZJLTdjPAjLVPun/9+18s+Jk avCA+7tOWoo+XIb3l4LzTct9HDpKAWgDcQUBa5wa8VkeX4F+OJ/Fspjkd/rqPo3bMFRw FBqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726679694; x=1727284494; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f408neNmJiHRMFNBITqjdfGcu6sd/hAmiLVrUqm2xBk=; b=vRhAPw15x1XM8u4bqvcnl79gDHBB5ZnwdFn+BYUmys/5nW2viw73WZvH0pQupH4AcV s1053z7g+H4ZTOjD0OhAtIc9bAk3W8KIZkmGceZXOjbkA22yhn9ZKShECdmmoies2DlV eDwE4PRHSvKrttZl0po4zb65fghID2ubjPj+EDX51ng4WAbHQiJQtvnOQ+I+mBjtCLFk HeK/j+Sgl4g0sFrHehjM173cBx5UTE1m+zfHGDNSfq+D5tEAlGu42/Gb6JIfrjySvEve y4MWaxhYANbZuw8LOHRIlywpB58k1JzUhUGh0LXfvPNDgY810yWRwEYoqgXvp3JPMZQ9 cfZg== X-Gm-Message-State: AOJu0YxZhXR6fmYWlDVx2QT4qu6F3e07n4eb1CXrZ57jBKPLSLg3Glia I0xw81u5EAj9HlYsm+4L4Xoc6mkbLfeXlnBLHBd9VWLuKX+Kc5PClh0Ox1uDTY9mAl3b7AGD2t8 wv/Yt+rB9tK3PvAa63kDwMBTAd3/Xp5hdBsVdKtfuwfSBqjqyYaMgv0M/5lVooHVJl0g5LvyUNk 9pOfZ4AxUeH2JgmbG/VGEwqJj8Z3LMsOLMV8kqIA== X-Google-Smtp-Source: AGHT+IGE90+JXk1/9HlzshqC/Q6QpcF2o6vJM8Xbn1n6a1qvv2LOTEKJguy44zgsNP1e6DDtTd2ABg== X-Received: by 2002:a05:6a21:1646:b0:1cf:3ec5:e779 with SMTP id adf61e73a8af0-1cf75d7fc8emr32031945637.5.1726679694350; Wed, 18 Sep 2024 10:14:54 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , richard.henderson@linaro.org, negge@google.com, Max Chou Subject: [PATCH v6 7/7] target/riscv: Inline unit-stride ld/st and corresponding functions for performance Date: Thu, 19 Sep 2024 01:14:12 +0800 Message-Id: <20240918171412.150107-8-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240918171412.150107-1-max.chou@sifive.com> References: <20240918171412.150107-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=max.chou@sifive.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1726679801806116600 Content-Type: text/plain; charset="utf-8" In the vector unit-stride load/store helper functions. the vext_ldst_us & vext_ldst_whole functions corresponding most of the execution time. Inline the functions can avoid the function call overhead to improve the helper function performance. Signed-off-by: Max Chou Reviewed-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza --- target/riscv/vector_helper.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 654d5e111f3..0d5ed950486 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -152,14 +152,16 @@ typedef void vext_ldst_elem_fn_tlb(CPURISCVState *env= , abi_ptr addr, typedef void vext_ldst_elem_fn_host(void *vd, uint32_t idx, void *host); =20 #define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \ -static void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \ +static inline QEMU_ALWAYS_INLINE \ +void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \ uint32_t idx, void *vd, uintptr_t retaddr) \ { \ ETYPE *cur =3D ((ETYPE *)vd + H(idx)); \ *cur =3D cpu_##LDSUF##_data_ra(env, addr, retaddr); \ } \ \ -static void NAME##_host(void *vd, uint32_t idx, void *host) \ +static inline QEMU_ALWAYS_INLINE \ +void NAME##_host(void *vd, uint32_t idx, void *host) \ { \ ETYPE *cur =3D ((ETYPE *)vd + H(idx)); \ *cur =3D (ETYPE)LDSUF##_p(host); \ @@ -171,14 +173,16 @@ GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl) GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq) =20 #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ -static void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \ +static inline QEMU_ALWAYS_INLINE \ +void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \ uint32_t idx, void *vd, uintptr_t retaddr) \ { \ ETYPE data =3D *((ETYPE *)vd + H(idx)); \ cpu_##STSUF##_data_ra(env, addr, data, retaddr); \ } \ \ -static void NAME##_host(void *vd, uint32_t idx, void *host) \ +static inline QEMU_ALWAYS_INLINE \ +void NAME##_host(void *vd, uint32_t idx, void *host) \ { \ ETYPE data =3D *((ETYPE *)vd + H(idx)); \ STSUF##_p(host, data); \ @@ -317,7 +321,7 @@ GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d_tlb) */ =20 /* unmasked unit-stride load and store operation */ -static void +static inline QEMU_ALWAYS_INLINE void vext_page_ldst_us(CPURISCVState *env, void *vd, target_ulong addr, uint32_t elems, uint32_t nf, uint32_t max_elems, uint32_t log2_esz, bool is_load, int mmu_index, @@ -369,7 +373,7 @@ vext_page_ldst_us(CPURISCVState *env, void *vd, target_= ulong addr, } } =20 -static void +static inline QEMU_ALWAYS_INLINE void vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t des= c, vext_ldst_elem_fn_tlb *ldst_tlb, vext_ldst_elem_fn_host *ldst_host, uint32_t log2_esz, @@ -756,7 +760,7 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d_tlb, lde_d_host) /* * load and store whole register instructions */ -static void +static inline QEMU_ALWAYS_INLINE void vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t = desc, vext_ldst_elem_fn_tlb *ldst_tlb, vext_ldst_elem_fn_host *ldst_host, uint32_t log2_esz, --=20 2.34.1