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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2dd608e2318sm1914577a91.32.2024.09.18.10.14.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2024 10:14:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1726679672; x=1727284472; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Nfs9IDqgQpVVigMZU11K8UdOmxP2QGM7nTxJBjJv74w=; b=nVjHBfRRHrSQaOhtW3UG2/JaqTM7Z7u6GNj/30UxNRmPySWwJo15aYIu8ZprACuiix etjmlT6dl4BV/UuSsW00PXB9wxaLdySZ9p9cQEBWwOc3MXjrOvqNkh9V/PiBMRQnGOSI o6lU45e1bm9SB58RDzSBESWfodYnZgl/nSSTHZeOTXzOM1ck/njwmmlIGxgSECRmFaRu 3Yt1Ayd4WLJdzgh0uVPLlxh3mFkLA8XKb4MqeJ/WuS3dS/pN+XaIgzTQJOgWoR5nOHHk EpcI7MjUdtUi0wcJgG+hbHJnJjQLC7AYbfot7EODpYynJF1b+F6pKXlncYZPzKZhyHWo onyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726679672; x=1727284472; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Nfs9IDqgQpVVigMZU11K8UdOmxP2QGM7nTxJBjJv74w=; b=Ic+zbPuArJ+V+bKjfyU8C2mQ7LhH9YyWOibQht4sfozceZ8Pr/e42HGeHAr7yrirkN ORSwFu6x5z/zoyAyGCbt5VEmOHHlMjeZ7A8qKFriCO19FmdCkBpuLmC1/k18knl/egug xXUZ59gfaFkZWPsUiyyk+hDFB9g0i/PZ99fljKv4EGbGpyMUhUTRNJG7SdG5LepmUxQ6 X43XolgjuZ6QxIZ75NMjFleqYuoySNeMJkj03dsaaFB/UZaIWWHKtXzg4EH43c4RhwGW pE+4Dnda8D7ldJ97Pdm23cFQFkypTexeze8UY7VObYP76R63qerr5jg2pS65kdI+v69R vQEw== X-Gm-Message-State: AOJu0YyIox9abWHo1z+qNWmOPjxg4MW6ozMKkhd5bwbwMQwc8yT7lMyM Xu/epWCIoJ4OUBVsKFjZG7GHB+Rx8yi3Uf8bY7Xqn4xHzOQjyHaIcSJMBroy5bzHzWawjKh/x1c F8oaoCWrfOTMh2EL4kzcyvzZOUS0DEZJEmgDi15ZN8Yx6rM1lgdR30OAYdn4KEGXpKN/o482m7i Ukl1AmiqgVufgaaSxrOmqqFVerIOQljtVeQv+7Ug== X-Google-Smtp-Source: AGHT+IGHoIu1KvtWHmKYThUD2uvco8vZFJarhXDHqX59sBe2QqGRkhQkFvNkNPLMJ2YsGEH+VsX7ww== X-Received: by 2002:a17:90a:d489:b0:2d3:cd57:bd3 with SMTP id 98e67ed59e1d1-2dbb9f3a7cemr28312007a91.29.1726679672383; Wed, 18 Sep 2024 10:14:32 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , richard.henderson@linaro.org, negge@google.com, Max Chou Subject: [PATCH v6 1/7] target/riscv: Set vdata.vm field for vector load/store whole register instructions Date: Thu, 19 Sep 2024 01:14:06 +0800 Message-Id: <20240918171412.150107-2-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240918171412.150107-1-max.chou@sifive.com> References: <20240918171412.150107-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=max.chou@sifive.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1726679737655116600 Content-Type: text/plain; charset="utf-8" The vm field of the vector load/store whole register instruction's encoding is 1. The helper function of the vector load/store whole register instructions may need the vdata.vm field to do some optimizations. Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 3a3896ba06c..14e10568bd7 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -770,6 +770,7 @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a= , uint8_t eew) /* Mask destination register are always tail-agnostic */ data =3D FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s); data =3D FIELD_DP32(data, VDATA, VMA, s->vma); + data =3D FIELD_DP32(data, VDATA, VM, 1); return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); } =20 @@ -787,6 +788,7 @@ static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a= , uint8_t eew) /* EMUL =3D 1, NFIELDS =3D 1 */ data =3D FIELD_DP32(data, VDATA, LMUL, 0); data =3D FIELD_DP32(data, VDATA, NF, 1); + data =3D FIELD_DP32(data, VDATA, VM, 1); return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); } =20 @@ -1106,6 +1108,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs= 1, uint32_t nf, TCGv_i32 desc; =20 uint32_t data =3D FIELD_DP32(0, VDATA, NF, nf); + data =3D FIELD_DP32(data, VDATA, VM, 1); dest =3D tcg_temp_new_ptr(); desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data)); --=20 2.34.1 From nobody Sun Nov 24 15:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1726679815; cv=none; d=zohomail.com; s=zohoarc; b=m8QXWvTBZ7H/mOFV1SQFJqUFn5RHgTjyZAMvzo1sHdGh8MPkSfbwO5Kxrev3CUyoYK4D7FRBp0ne0IHeKtD9PPtnOobsXusDfaW+NVO44gaKuJ1eFIs59SwpdqOxvlZL3BLKz3zFWYPzfrDO/YOsAAvv1WO2qYXQhlqLPHmbPzI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726679815; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2gLczlRjPI9o0y3XIHKzhobqyXKG8O1cfEkc+jreqI0=; b=KN0GFmxjb0LodONTmyjeek+X0mikt7WcnhrW90M/teNDgFQ+/XVCuejO8zWaIRunsuBL0lPLKB/rs/KfZhgtawNlleoYN426GX83qBfHQ8mj5oXoHpvXhpWpe4ITB36rpRA5kr5Xz7Io+pTn6bpkkv3ZmEE3kLU4gcjSWtK/5V4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726679815180764.2591108478354; Wed, 18 Sep 2024 10:16:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sqyGO-00071f-3q; Wed, 18 Sep 2024 13:14:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sqyGG-0006p3-Dy for qemu-devel@nongnu.org; Wed, 18 Sep 2024 13:14:41 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sqyGE-0001rd-87 for qemu-devel@nongnu.org; Wed, 18 Sep 2024 13:14:40 -0400 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-7c6b4222fe3so4597060a12.3 for ; Wed, 18 Sep 2024 10:14:37 -0700 (PDT) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. [114.35.142.126]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2dd608e2318sm1914577a91.32.2024.09.18.10.14.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2024 10:14:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1726679677; x=1727284477; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2gLczlRjPI9o0y3XIHKzhobqyXKG8O1cfEkc+jreqI0=; b=TQm1WYqMRqmwT9sSvxmFIqoQUFOWbsnW+cTz1dI6pocDHIEHsjsvT9wSOHwGKLLExN gd/pc16hdxTRZGsbl3wFcO3AbRNWCymFVOrm9/tD/etVmjDOVztA38u6BlFvefF5So1l OPbvYRp4uN9KF9wR9tscFd1OzL2Y/aORS85wsMBdYqKX1Ni9hYl1wlRB1mglXyZ/FsZN Y8t7GWB+zxenQsgEgbNl4PDU/wMbXs3shbD6q6/NVpz/CpUe++Bou6OzNE26XEZXXjPb ZJqxmIjfZg/SXMTtpKZjXA3kQtQZNeqbJyqm/ZD14xB/OwCO0ZcAKn7StCD2Tc9yOpdD Fwjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726679677; x=1727284477; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2gLczlRjPI9o0y3XIHKzhobqyXKG8O1cfEkc+jreqI0=; b=PJeziWSkA1Kc+bix8IBRIQTRInp/FoPlWOFdtaIcYOZptPvIn//oqrMIEFcoJ4HhqX HNJFetj/fHGjxm1GMhzgDEXd64FzHe5AtObiJST+f0k5/MvnVxo7dlfl0olrieARp2EW qHDVbjRw72CLY/aGULWbJjtwxt678vGnMnBpiM0d6IVxZGlCtbPa0CT3ID/piQKO24RZ rZPGz4gQBBUw0AA0uIoNmaeIqF/58vFPlIEWU3v4CuUIkKuEukkKotc9ORbIZaqQ4zO5 q0XG5bKXTRp2VdHRJYVPDmRsI7A7dPq7J2rvEP2+i/jcyO5UZ52hx4N4apaQTPslZhCq nNxw== X-Gm-Message-State: AOJu0Yxscrt4Az0NXO7Jnlk3fL41ng/gA6ENhklAHyQAVYFG/MmmiSuw xUocVlNjL5q7vrJTd6Im61Ee1zd4GLvlf6T1JOn36fbplvrPhBSapljEigJVY5dbVIBXhDJhIuW Ltq/vSbVpmZIsS6RBOollqvd9xsVxOfGgHelpouA8t7gCHo1GvUuL0Sb4/wwSU2QsLcmg3KEJku FaDIvl2r0LJdvINAYA+h2ShUJCfwEmt0XS4liQqg== X-Google-Smtp-Source: AGHT+IG9fL0f4YjbvrVsmY4IypiDn4mL9Xw7TrF4Zx852mj7hIWgHSy74hJgkAau6piqxzNL2tnLNg== X-Received: by 2002:a17:90a:6d27:b0:2d8:8a04:1b16 with SMTP id 98e67ed59e1d1-2dba0080957mr27383325a91.33.1726679676530; Wed, 18 Sep 2024 10:14:36 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , richard.henderson@linaro.org, negge@google.com, Max Chou Subject: [PATCH v6 2/7] target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us Date: Thu, 19 Sep 2024 01:14:07 +0800 Message-Id: <20240918171412.150107-3-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240918171412.150107-1-max.chou@sifive.com> References: <20240918171412.150107-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=max.chou@sifive.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1726679815873116600 Content-Type: text/plain; charset="utf-8" Because the real vl (evl) of vext_ldst_us may be different (e.g. vlm.v/vsm.v/etc.), so the VSTART_CHECK_EARLY_EXIT checking function should be replaced by checking evl in vext_ldst_us. Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/vector_helper.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 87d2399c7e3..967bb2687ae 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -276,7 +276,10 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVStat= e *env, uint32_t desc, uint32_t max_elems =3D vext_max_elems(desc, log2_esz); uint32_t esz =3D 1 << log2_esz; =20 - VSTART_CHECK_EARLY_EXIT(env); + if (env->vstart >=3D evl) { + env->vstart =3D 0; + return; + } =20 /* load bytes from guest memory */ for (i =3D env->vstart; i < evl; env->vstart =3D ++i) { --=20 2.34.1 From nobody Sun Nov 24 15:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1726679748; cv=none; d=zohomail.com; s=zohoarc; b=nDZno4wKiqmpPGvVA0D3GzlwR81mNtKC4+mLBsrJLDvLrK43H/5pi0a3VDWdL2Ee+AAGfF5Onv7r9U1UmYjMoFYmcQM0ZnQrnAzrm6ffecH0dGAIpJE9DSB3Wq0ONMWqvJEeOQAJejxIXukHfnwp7gWnBb9NfKmEGNB44cTot6U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726679748; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=M6LEzHTIKfl00G8sbiHdw7NG2hDNTj2rDJZBBWEdaHA=; b=PqwXYG/v8vmrV0E0MxWXtV7QFDKmZHJjZviDSDFXGRPAPhsLPZOmrxEXGTxWT7Yjv6fpPhElZqzkF3+Taq2Ap/GCAAISkr94bN9UnLlTKyNn1G/rsbFiYoCxuf6zwp/Phah/0Gt6CFmzBMRIhyt2TnLc0PHdyO9aZW92CRCqwQ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726679748039128.45059689344737; Wed, 18 Sep 2024 10:15:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sqyGQ-0007B3-MF; Wed, 18 Sep 2024 13:14:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sqyGN-0006zO-91 for qemu-devel@nongnu.org; Wed, 18 Sep 2024 13:14:47 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sqyGJ-0001sA-HH for qemu-devel@nongnu.org; Wed, 18 Sep 2024 13:14:46 -0400 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-2da55ea8163so791a91.1 for ; Wed, 18 Sep 2024 10:14:43 -0700 (PDT) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. [114.35.142.126]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2dd608e2318sm1914577a91.32.2024.09.18.10.14.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2024 10:14:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1726679682; x=1727284482; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M6LEzHTIKfl00G8sbiHdw7NG2hDNTj2rDJZBBWEdaHA=; b=KMimPAeZEqQB+zw8o+zHjzkEEJfGrfD21B4zmIoAIB3CD/B9bFOlOWJLGKKVbP43zE Nnd5eW/DKzOTkHfh3ut7Mb2umRcy9YwH445svi6GTkGDXO/956m15id/DWOD+bNm65Dk jVQPKnN5j60o1S4CwI3++mvO3A7AENj6uoeyM68Dnvn2ZiqkV2U+ABqWC7ELiQ64f009 hvK0RW/oVcaR80LzRyBqU4n1ZI7V+NXb+wCib94aVE+s/9T7LNgtDVULcy7xGHzd0nNE HU/CVqNCFxiA9fkam95Nook9YC1J8EUWQD5b/llFroFiWrhWFbH7Fj7o41E69B4XoKLU m7eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726679682; x=1727284482; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M6LEzHTIKfl00G8sbiHdw7NG2hDNTj2rDJZBBWEdaHA=; b=QRBJLqk/VKhDF2P5sET3bcd3uvQTZogi1wYNNr2QkYUeMojOVWLROwghAXJUlGv9Wi JuT5zVzvHeH2r7wD94NL5VEQPdQOlkW4FMIKBqz6Wjc/9Cscc1gvNctbujxdPNqMhhUA Ltb+rf6Atx+eIToxMf6ixHyKPq0FAKhn/kL/xSuwZLHmyRFy4Zd1nyY8/r9nh8RZlYNc Iw6OQOv8LCEYQb8V/zPqHwjyTBsDc0n/XVeJJAQovlY/ZIyPUxZ2IZ3of1AFu+65lT6K f9VfzwuEEdoqBrMFwZDS18tZdUpC1EEsqPP/dziO9ZRX268Z0JcWSoL+m35E3KEtSsvE quXw== X-Gm-Message-State: AOJu0YzlL9nWtHx59iVolNRqMCJZNulz97IadYf7Igvr6iHUaszYyLwH rmG59MvIrHdtmkPXzrCUPqLNvTyivuHGHjm7CIiJlX+9JKDAVDob/xZVCYeOgjgqtbcL78CWezQ E2BjcGF/pNtvVi7cUdWZpLw40RGF/Mgm9kYOWK+0Mt3VXCH1vM5qLIWt1n6yA4VYKpUciFC4wBJ 9dzciub9UkD5Jn8dftkDfcP5hm6et3HxfNBUL5hw== X-Google-Smtp-Source: AGHT+IHbWv/kdWxiYUUxhaHZ0z8zBwoJRDUTLmBMoemUSwoEcoypjJvaSZp87Y4KmDzbPZfG2n4H4Q== X-Received: by 2002:a17:90a:2f23:b0:2d8:82a2:b093 with SMTP id 98e67ed59e1d1-2db9ffcaab5mr26527347a91.13.1726679681322; Wed, 18 Sep 2024 10:14:41 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , richard.henderson@linaro.org, negge@google.com, Max Chou Subject: [PATCH v6 3/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store Date: Thu, 19 Sep 2024 01:14:08 +0800 Message-Id: <20240918171412.150107-4-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240918171412.150107-1-max.chou@sifive.com> References: <20240918171412.150107-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=max.chou@sifive.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1726679749653116600 Content-Type: text/plain; charset="utf-8" This commit references the sve_ldN_r/sve_stN_r helper functions in ARM target to optimize the vector unmasked unit-stride load/store implementation with following optimizations: * Get the page boundary * Probing pages/resolving host memory address at the beginning if possible * Provide new interface to direct access host memory * Switch to the original slow TLB access when cross page element/violate page permission/violate pmp/watchpoints in page The original element load/store interface is replaced by the new element load/store functions with _tlb & _host postfix that means doing the element load/store through the original softmmu flow and the direct access host memory flow. Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/vector_helper.c | 363 +++++++++++++++++++++-------------- 1 file changed, 224 insertions(+), 139 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 967bb2687ae..c2fcf8b3a00 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -147,34 +147,47 @@ static inline void vext_set_elem_mask(void *v0, int i= ndex, } =20 /* elements operations for load and store */ -typedef void vext_ldst_elem_fn(CPURISCVState *env, abi_ptr addr, - uint32_t idx, void *vd, uintptr_t retaddr); +typedef void vext_ldst_elem_fn_tlb(CPURISCVState *env, abi_ptr addr, + uint32_t idx, void *vd, uintptr_t retad= dr); +typedef void vext_ldst_elem_fn_host(void *vd, uint32_t idx, void *host); =20 -#define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \ -static void NAME(CPURISCVState *env, abi_ptr addr, \ - uint32_t idx, void *vd, uintptr_t retaddr)\ -{ \ - ETYPE *cur =3D ((ETYPE *)vd + H(idx)); \ - *cur =3D cpu_##LDSUF##_data_ra(env, addr, retaddr); \ -} \ - -GEN_VEXT_LD_ELEM(lde_b, int8_t, H1, ldsb) -GEN_VEXT_LD_ELEM(lde_h, int16_t, H2, ldsw) -GEN_VEXT_LD_ELEM(lde_w, int32_t, H4, ldl) -GEN_VEXT_LD_ELEM(lde_d, int64_t, H8, ldq) - -#define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ -static void NAME(CPURISCVState *env, abi_ptr addr, \ - uint32_t idx, void *vd, uintptr_t retaddr)\ -{ \ - ETYPE data =3D *((ETYPE *)vd + H(idx)); \ - cpu_##STSUF##_data_ra(env, addr, data, retaddr); \ +#define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \ +static void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \ + uint32_t idx, void *vd, uintptr_t retaddr) \ +{ \ + ETYPE *cur =3D ((ETYPE *)vd + H(idx)); \ + *cur =3D cpu_##LDSUF##_data_ra(env, addr, retaddr); \ +} \ + \ +static void NAME##_host(void *vd, uint32_t idx, void *host) \ +{ \ + ETYPE *cur =3D ((ETYPE *)vd + H(idx)); \ + *cur =3D (ETYPE)LDSUF##_p(host); \ +} + +GEN_VEXT_LD_ELEM(lde_b, uint8_t, H1, ldub) +GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw) +GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl) +GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq) + +#define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ +static void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \ + uint32_t idx, void *vd, uintptr_t retaddr) \ +{ \ + ETYPE data =3D *((ETYPE *)vd + H(idx)); \ + cpu_##STSUF##_data_ra(env, addr, data, retaddr); \ +} \ + \ +static void NAME##_host(void *vd, uint32_t idx, void *host) \ +{ \ + ETYPE data =3D *((ETYPE *)vd + H(idx)); \ + STSUF##_p(host, data); \ } =20 -GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb) -GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw) -GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl) -GEN_VEXT_ST_ELEM(ste_d, int64_t, H8, stq) +GEN_VEXT_ST_ELEM(ste_b, uint8_t, H1, stb) +GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw) +GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl) +GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq) =20 static void vext_set_tail_elems_1s(target_ulong vl, void *vd, uint32_t desc, uint32_t nf, @@ -197,11 +210,10 @@ static void vext_set_tail_elems_1s(target_ulong vl, v= oid *vd, * stride: access vector element from strided memory */ static void -vext_ldst_stride(void *vd, void *v0, target_ulong base, - target_ulong stride, CPURISCVState *env, - uint32_t desc, uint32_t vm, - vext_ldst_elem_fn *ldst_elem, - uint32_t log2_esz, uintptr_t ra) +vext_ldst_stride(void *vd, void *v0, target_ulong base, target_ulong strid= e, + CPURISCVState *env, uint32_t desc, uint32_t vm, + vext_ldst_elem_fn_tlb *ldst_elem, uint32_t log2_esz, + uintptr_t ra) { uint32_t i, k; uint32_t nf =3D vext_nf(desc); @@ -241,10 +253,10 @@ void HELPER(NAME)(void *vd, void * v0, target_ulong b= ase, \ ctzl(sizeof(ETYPE)), GETPC()); \ } =20 -GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b) -GEN_VEXT_LD_STRIDE(vlse16_v, int16_t, lde_h) -GEN_VEXT_LD_STRIDE(vlse32_v, int32_t, lde_w) -GEN_VEXT_LD_STRIDE(vlse64_v, int64_t, lde_d) +GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b_tlb) +GEN_VEXT_LD_STRIDE(vlse16_v, int16_t, lde_h_tlb) +GEN_VEXT_LD_STRIDE(vlse32_v, int32_t, lde_w_tlb) +GEN_VEXT_LD_STRIDE(vlse64_v, int64_t, lde_d_tlb) =20 #define GEN_VEXT_ST_STRIDE(NAME, ETYPE, STORE_FN) \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ @@ -256,42 +268,114 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong b= ase, \ ctzl(sizeof(ETYPE)), GETPC()); \ } =20 -GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b) -GEN_VEXT_ST_STRIDE(vsse16_v, int16_t, ste_h) -GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w) -GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d) +GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b_tlb) +GEN_VEXT_ST_STRIDE(vsse16_v, int16_t, ste_h_tlb) +GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w_tlb) +GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d_tlb) =20 /* * unit-stride: access elements stored contiguously in memory */ =20 /* unmasked unit-stride load and store operation */ +static void +vext_page_ldst_us(CPURISCVState *env, void *vd, target_ulong addr, + uint32_t elems, uint32_t nf, uint32_t max_elems, + uint32_t log2_esz, bool is_load, int mmu_index, + vext_ldst_elem_fn_tlb *ldst_tlb, + vext_ldst_elem_fn_host *ldst_host, uintptr_t ra) +{ + void *host; + int i, k, flags; + uint32_t esz =3D 1 << log2_esz; + uint32_t size =3D (elems * nf) << log2_esz; + uint32_t evl =3D env->vstart + elems; + MMUAccessType access_type =3D is_load ? MMU_DATA_LOAD : MMU_DATA_STORE; + + /* Check page permission/pmp/watchpoint/etc. */ + flags =3D probe_access_flags(env, adjust_addr(env, addr), size, access= _type, + mmu_index, true, &host, ra); + + if (flags =3D=3D 0) { + for (i =3D env->vstart; i < evl; ++i) { + k =3D 0; + while (k < nf) { + ldst_host(vd, i + k * max_elems, host); + host +=3D esz; + k++; + } + } + env->vstart +=3D elems; + } else { + /* load bytes from guest memory */ + for (i =3D env->vstart; i < evl; env->vstart =3D ++i) { + k =3D 0; + while (k < nf) { + ldst_tlb(env, adjust_addr(env, addr), i + k * max_elems, v= d, + ra); + addr +=3D esz; + k++; + } + } + } +} + static void vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t des= c, - vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uint32_t evl, - uintptr_t ra) + vext_ldst_elem_fn_tlb *ldst_tlb, + vext_ldst_elem_fn_host *ldst_host, uint32_t log2_esz, + uint32_t evl, uintptr_t ra, bool is_load) { - uint32_t i, k; + uint32_t k; + target_ulong page_split, elems, addr; uint32_t nf =3D vext_nf(desc); uint32_t max_elems =3D vext_max_elems(desc, log2_esz); uint32_t esz =3D 1 << log2_esz; + uint32_t msize =3D nf * esz; + int mmu_index =3D riscv_env_mmu_index(env, false); =20 if (env->vstart >=3D evl) { env->vstart =3D 0; return; } =20 - /* load bytes from guest memory */ - for (i =3D env->vstart; i < evl; env->vstart =3D ++i) { - k =3D 0; - while (k < nf) { - target_ulong addr =3D base + ((i * nf + k) << log2_esz); - ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, = ra); - k++; + /* Calculate the page range of first page */ + addr =3D base + ((env->vstart * nf) << log2_esz); + page_split =3D -(addr | TARGET_PAGE_MASK); + /* Get number of elements */ + elems =3D page_split / msize; + if (unlikely(env->vstart + elems >=3D evl)) { + elems =3D evl - env->vstart; + } + + /* Load/store elements in the first page */ + if (likely(elems)) { + vext_page_ldst_us(env, vd, addr, elems, nf, max_elems, log2_esz, + is_load, mmu_index, ldst_tlb, ldst_host, ra); + } + + /* Load/store elements in the second page */ + if (unlikely(env->vstart < evl)) { + /* Cross page element */ + if (unlikely(page_split % msize)) { + for (k =3D 0; k < nf; k++) { + addr =3D base + ((env->vstart * nf + k) << log2_esz); + ldst_tlb(env, adjust_addr(env, addr), + env->vstart + k * max_elems, vd, ra); + } + env->vstart++; } + + addr =3D base + ((env->vstart * nf) << log2_esz); + /* Get number of elements of second page */ + elems =3D evl - env->vstart; + + /* Load/store elements in the second page */ + vext_page_ldst_us(env, vd, addr, elems, nf, max_elems, log2_esz, + is_load, mmu_index, ldst_tlb, ldst_host, ra); } - env->vstart =3D 0; =20 + env->vstart =3D 0; vext_set_tail_elems_1s(evl, vd, desc, nf, esz, max_elems); } =20 @@ -300,47 +384,47 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVSta= te *env, uint32_t desc, * stride, stride =3D NF * sizeof (ETYPE) */ =20 -#define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN) \ -void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t stride =3D vext_nf(desc) << ctzl(sizeof(ETYPE)); \ - vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \ - ctzl(sizeof(ETYPE)), GETPC()); \ -} \ - \ -void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - vext_ldst_us(vd, base, env, desc, LOAD_FN, \ - ctzl(sizeof(ETYPE)), env->vl, GETPC()); \ +#define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN_TLB, LOAD_FN_HOST) \ +void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t stride =3D vext_nf(desc) << ctzl(sizeof(ETYPE)); \ + vext_ldst_stride(vd, v0, base, stride, env, desc, false, \ + LOAD_FN_TLB, ctzl(sizeof(ETYPE)), GETPC()); \ +} \ + \ +void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldst_us(vd, base, env, desc, LOAD_FN_TLB, LOAD_FN_HOST, \ + ctzl(sizeof(ETYPE)), env->vl, GETPC(), true); \ } =20 -GEN_VEXT_LD_US(vle8_v, int8_t, lde_b) -GEN_VEXT_LD_US(vle16_v, int16_t, lde_h) -GEN_VEXT_LD_US(vle32_v, int32_t, lde_w) -GEN_VEXT_LD_US(vle64_v, int64_t, lde_d) +GEN_VEXT_LD_US(vle8_v, int8_t, lde_b_tlb, lde_b_host) +GEN_VEXT_LD_US(vle16_v, int16_t, lde_h_tlb, lde_h_host) +GEN_VEXT_LD_US(vle32_v, int32_t, lde_w_tlb, lde_w_host) +GEN_VEXT_LD_US(vle64_v, int64_t, lde_d_tlb, lde_d_host) =20 -#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \ +#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN_TLB, STORE_FN_HOST) \ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t stride =3D vext_nf(desc) << ctzl(sizeof(ETYPE)); = \ - vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \ - ctzl(sizeof(ETYPE)), GETPC()); \ + vext_ldst_stride(vd, v0, base, stride, env, desc, false, \ + STORE_FN_TLB, ctzl(sizeof(ETYPE)), GETPC()); \ } \ \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ - vext_ldst_us(vd, base, env, desc, STORE_FN, \ - ctzl(sizeof(ETYPE)), env->vl, GETPC()); \ + vext_ldst_us(vd, base, env, desc, STORE_FN_TLB, STORE_FN_HOST, \ + ctzl(sizeof(ETYPE)), env->vl, GETPC(), false); \ } =20 -GEN_VEXT_ST_US(vse8_v, int8_t, ste_b) -GEN_VEXT_ST_US(vse16_v, int16_t, ste_h) -GEN_VEXT_ST_US(vse32_v, int32_t, ste_w) -GEN_VEXT_ST_US(vse64_v, int64_t, ste_d) +GEN_VEXT_ST_US(vse8_v, int8_t, ste_b_tlb, ste_b_host) +GEN_VEXT_ST_US(vse16_v, int16_t, ste_h_tlb, ste_h_host) +GEN_VEXT_ST_US(vse32_v, int32_t, ste_w_tlb, ste_w_host) +GEN_VEXT_ST_US(vse64_v, int64_t, ste_d_tlb, ste_d_host) =20 /* * unit stride mask load and store, EEW =3D 1 @@ -350,8 +434,8 @@ void HELPER(vlm_v)(void *vd, void *v0, target_ulong bas= e, { /* evl =3D ceil(vl/8) */ uint8_t evl =3D (env->vl + 7) >> 3; - vext_ldst_us(vd, base, env, desc, lde_b, - 0, evl, GETPC()); + vext_ldst_us(vd, base, env, desc, lde_b_tlb, lde_b_host, + 0, evl, GETPC(), true); } =20 void HELPER(vsm_v)(void *vd, void *v0, target_ulong base, @@ -359,8 +443,8 @@ void HELPER(vsm_v)(void *vd, void *v0, target_ulong bas= e, { /* evl =3D ceil(vl/8) */ uint8_t evl =3D (env->vl + 7) >> 3; - vext_ldst_us(vd, base, env, desc, ste_b, - 0, evl, GETPC()); + vext_ldst_us(vd, base, env, desc, ste_b_tlb, ste_b_host, + 0, evl, GETPC(), false); } =20 /* @@ -385,7 +469,7 @@ static inline void vext_ldst_index(void *vd, void *v0, target_ulong base, void *vs2, CPURISCVState *env, uint32_t desc, vext_get_index_addr get_index_addr, - vext_ldst_elem_fn *ldst_elem, + vext_ldst_elem_fn_tlb *ldst_elem, uint32_t log2_esz, uintptr_t ra) { uint32_t i, k; @@ -426,22 +510,22 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong ba= se, \ LOAD_FN, ctzl(sizeof(ETYPE)), GETPC()); = \ } =20 -GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b) -GEN_VEXT_LD_INDEX(vlxei8_16_v, int16_t, idx_b, lde_h) -GEN_VEXT_LD_INDEX(vlxei8_32_v, int32_t, idx_b, lde_w) -GEN_VEXT_LD_INDEX(vlxei8_64_v, int64_t, idx_b, lde_d) -GEN_VEXT_LD_INDEX(vlxei16_8_v, int8_t, idx_h, lde_b) -GEN_VEXT_LD_INDEX(vlxei16_16_v, int16_t, idx_h, lde_h) -GEN_VEXT_LD_INDEX(vlxei16_32_v, int32_t, idx_h, lde_w) -GEN_VEXT_LD_INDEX(vlxei16_64_v, int64_t, idx_h, lde_d) -GEN_VEXT_LD_INDEX(vlxei32_8_v, int8_t, idx_w, lde_b) -GEN_VEXT_LD_INDEX(vlxei32_16_v, int16_t, idx_w, lde_h) -GEN_VEXT_LD_INDEX(vlxei32_32_v, int32_t, idx_w, lde_w) -GEN_VEXT_LD_INDEX(vlxei32_64_v, int64_t, idx_w, lde_d) -GEN_VEXT_LD_INDEX(vlxei64_8_v, int8_t, idx_d, lde_b) -GEN_VEXT_LD_INDEX(vlxei64_16_v, int16_t, idx_d, lde_h) -GEN_VEXT_LD_INDEX(vlxei64_32_v, int32_t, idx_d, lde_w) -GEN_VEXT_LD_INDEX(vlxei64_64_v, int64_t, idx_d, lde_d) +GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b_tlb) +GEN_VEXT_LD_INDEX(vlxei8_16_v, int16_t, idx_b, lde_h_tlb) +GEN_VEXT_LD_INDEX(vlxei8_32_v, int32_t, idx_b, lde_w_tlb) +GEN_VEXT_LD_INDEX(vlxei8_64_v, int64_t, idx_b, lde_d_tlb) +GEN_VEXT_LD_INDEX(vlxei16_8_v, int8_t, idx_h, lde_b_tlb) +GEN_VEXT_LD_INDEX(vlxei16_16_v, int16_t, idx_h, lde_h_tlb) +GEN_VEXT_LD_INDEX(vlxei16_32_v, int32_t, idx_h, lde_w_tlb) +GEN_VEXT_LD_INDEX(vlxei16_64_v, int64_t, idx_h, lde_d_tlb) +GEN_VEXT_LD_INDEX(vlxei32_8_v, int8_t, idx_w, lde_b_tlb) +GEN_VEXT_LD_INDEX(vlxei32_16_v, int16_t, idx_w, lde_h_tlb) +GEN_VEXT_LD_INDEX(vlxei32_32_v, int32_t, idx_w, lde_w_tlb) +GEN_VEXT_LD_INDEX(vlxei32_64_v, int64_t, idx_w, lde_d_tlb) +GEN_VEXT_LD_INDEX(vlxei64_8_v, int8_t, idx_d, lde_b_tlb) +GEN_VEXT_LD_INDEX(vlxei64_16_v, int16_t, idx_d, lde_h_tlb) +GEN_VEXT_LD_INDEX(vlxei64_32_v, int32_t, idx_d, lde_w_tlb) +GEN_VEXT_LD_INDEX(vlxei64_64_v, int64_t, idx_d, lde_d_tlb) =20 #define GEN_VEXT_ST_INDEX(NAME, ETYPE, INDEX_FN, STORE_FN) \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ @@ -452,22 +536,22 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong ba= se, \ GETPC()); \ } =20 -GEN_VEXT_ST_INDEX(vsxei8_8_v, int8_t, idx_b, ste_b) -GEN_VEXT_ST_INDEX(vsxei8_16_v, int16_t, idx_b, ste_h) -GEN_VEXT_ST_INDEX(vsxei8_32_v, int32_t, idx_b, ste_w) -GEN_VEXT_ST_INDEX(vsxei8_64_v, int64_t, idx_b, ste_d) -GEN_VEXT_ST_INDEX(vsxei16_8_v, int8_t, idx_h, ste_b) -GEN_VEXT_ST_INDEX(vsxei16_16_v, int16_t, idx_h, ste_h) -GEN_VEXT_ST_INDEX(vsxei16_32_v, int32_t, idx_h, ste_w) -GEN_VEXT_ST_INDEX(vsxei16_64_v, int64_t, idx_h, ste_d) -GEN_VEXT_ST_INDEX(vsxei32_8_v, int8_t, idx_w, ste_b) -GEN_VEXT_ST_INDEX(vsxei32_16_v, int16_t, idx_w, ste_h) -GEN_VEXT_ST_INDEX(vsxei32_32_v, int32_t, idx_w, ste_w) -GEN_VEXT_ST_INDEX(vsxei32_64_v, int64_t, idx_w, ste_d) -GEN_VEXT_ST_INDEX(vsxei64_8_v, int8_t, idx_d, ste_b) -GEN_VEXT_ST_INDEX(vsxei64_16_v, int16_t, idx_d, ste_h) -GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w) -GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d) +GEN_VEXT_ST_INDEX(vsxei8_8_v, int8_t, idx_b, ste_b_tlb) +GEN_VEXT_ST_INDEX(vsxei8_16_v, int16_t, idx_b, ste_h_tlb) +GEN_VEXT_ST_INDEX(vsxei8_32_v, int32_t, idx_b, ste_w_tlb) +GEN_VEXT_ST_INDEX(vsxei8_64_v, int64_t, idx_b, ste_d_tlb) +GEN_VEXT_ST_INDEX(vsxei16_8_v, int8_t, idx_h, ste_b_tlb) +GEN_VEXT_ST_INDEX(vsxei16_16_v, int16_t, idx_h, ste_h_tlb) +GEN_VEXT_ST_INDEX(vsxei16_32_v, int32_t, idx_h, ste_w_tlb) +GEN_VEXT_ST_INDEX(vsxei16_64_v, int64_t, idx_h, ste_d_tlb) +GEN_VEXT_ST_INDEX(vsxei32_8_v, int8_t, idx_w, ste_b_tlb) +GEN_VEXT_ST_INDEX(vsxei32_16_v, int16_t, idx_w, ste_h_tlb) +GEN_VEXT_ST_INDEX(vsxei32_32_v, int32_t, idx_w, ste_w_tlb) +GEN_VEXT_ST_INDEX(vsxei32_64_v, int64_t, idx_w, ste_d_tlb) +GEN_VEXT_ST_INDEX(vsxei64_8_v, int8_t, idx_d, ste_b_tlb) +GEN_VEXT_ST_INDEX(vsxei64_16_v, int16_t, idx_d, ste_h_tlb) +GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w_tlb) +GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d_tlb) =20 /* * unit-stride fault-only-fisrt load instructions @@ -475,7 +559,7 @@ GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d) static inline void vext_ldff(void *vd, void *v0, target_ulong base, CPURISCVState *env, uint32_t desc, - vext_ldst_elem_fn *ldst_elem, + vext_ldst_elem_fn_tlb *ldst_elem, uint32_t log2_esz, uintptr_t ra) { uint32_t i, k, vl =3D 0; @@ -561,10 +645,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong ba= se, \ ctzl(sizeof(ETYPE)), GETPC()); \ } =20 -GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b) -GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h) -GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w) -GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d) +GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b_tlb) +GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h_tlb) +GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w_tlb) +GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d_tlb) =20 #define DO_SWAP(N, M) (M) #define DO_AND(N, M) (N & M) @@ -581,7 +665,8 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d) */ static void vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t = desc, - vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uintptr_t= ra) + vext_ldst_elem_fn_tlb *ldst_elem, uint32_t log2_esz, + uintptr_t ra) { uint32_t i, k, off, pos; uint32_t nf =3D vext_nf(desc); @@ -625,22 +710,22 @@ void HELPER(NAME)(void *vd, target_ulong base, \ ctzl(sizeof(ETYPE)), GETPC()); \ } =20 -GEN_VEXT_LD_WHOLE(vl1re8_v, int8_t, lde_b) -GEN_VEXT_LD_WHOLE(vl1re16_v, int16_t, lde_h) -GEN_VEXT_LD_WHOLE(vl1re32_v, int32_t, lde_w) -GEN_VEXT_LD_WHOLE(vl1re64_v, int64_t, lde_d) -GEN_VEXT_LD_WHOLE(vl2re8_v, int8_t, lde_b) -GEN_VEXT_LD_WHOLE(vl2re16_v, int16_t, lde_h) -GEN_VEXT_LD_WHOLE(vl2re32_v, int32_t, lde_w) -GEN_VEXT_LD_WHOLE(vl2re64_v, int64_t, lde_d) -GEN_VEXT_LD_WHOLE(vl4re8_v, int8_t, lde_b) -GEN_VEXT_LD_WHOLE(vl4re16_v, int16_t, lde_h) -GEN_VEXT_LD_WHOLE(vl4re32_v, int32_t, lde_w) -GEN_VEXT_LD_WHOLE(vl4re64_v, int64_t, lde_d) -GEN_VEXT_LD_WHOLE(vl8re8_v, int8_t, lde_b) -GEN_VEXT_LD_WHOLE(vl8re16_v, int16_t, lde_h) -GEN_VEXT_LD_WHOLE(vl8re32_v, int32_t, lde_w) -GEN_VEXT_LD_WHOLE(vl8re64_v, int64_t, lde_d) +GEN_VEXT_LD_WHOLE(vl1re8_v, int8_t, lde_b_tlb) +GEN_VEXT_LD_WHOLE(vl1re16_v, int16_t, lde_h_tlb) +GEN_VEXT_LD_WHOLE(vl1re32_v, int32_t, lde_w_tlb) +GEN_VEXT_LD_WHOLE(vl1re64_v, int64_t, lde_d_tlb) +GEN_VEXT_LD_WHOLE(vl2re8_v, int8_t, lde_b_tlb) +GEN_VEXT_LD_WHOLE(vl2re16_v, int16_t, lde_h_tlb) +GEN_VEXT_LD_WHOLE(vl2re32_v, int32_t, lde_w_tlb) +GEN_VEXT_LD_WHOLE(vl2re64_v, int64_t, lde_d_tlb) +GEN_VEXT_LD_WHOLE(vl4re8_v, int8_t, lde_b_tlb) +GEN_VEXT_LD_WHOLE(vl4re16_v, int16_t, lde_h_tlb) +GEN_VEXT_LD_WHOLE(vl4re32_v, int32_t, lde_w_tlb) +GEN_VEXT_LD_WHOLE(vl4re64_v, int64_t, lde_d_tlb) +GEN_VEXT_LD_WHOLE(vl8re8_v, int8_t, lde_b_tlb) +GEN_VEXT_LD_WHOLE(vl8re16_v, int16_t, lde_h_tlb) +GEN_VEXT_LD_WHOLE(vl8re32_v, int32_t, lde_w_tlb) +GEN_VEXT_LD_WHOLE(vl8re64_v, int64_t, lde_d_tlb) =20 #define GEN_VEXT_ST_WHOLE(NAME, ETYPE, STORE_FN) \ void HELPER(NAME)(void *vd, target_ulong base, \ @@ -650,10 +735,10 @@ void HELPER(NAME)(void *vd, target_ulong base, \ ctzl(sizeof(ETYPE)), GETPC()); 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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2dd608e2318sm1914577a91.32.2024.09.18.10.14.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2024 10:14:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1726679685; x=1727284485; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+Yad8rwljItd1lBOHF5l5s1r+xJNloMy2zxgaSK2408=; b=iivNQSNuAS4ATLOyxwEViiJUowCSZcTN+Ar8VK2PnaiIHjbWLOojqZ4egIGJGnABFv bqIehIhu2QdXjFlfiM7zcg1IUo/HC4LOs3PrmVq2B6jHt+AVaLSV58yyzKxDNsUCumjG I+VNEkIkwCdbJlPBbRr/A/kw3dcoHTwf/buVj9Qcb8flkK083Axp6GpjdDdDcHNxX8m6 n8n7icYFch2BIyYrj+fiG0xTLWnUjn3c5+AZG125kudOYEtlFOlM8IQVwOeywsSDMe08 HMabrKqPP2B8jhFFMGMHsIBn0iFtIQ/Ab6CfE6yxohzJY1fIKH0Et0a23sAKJxEsfJZw m/Hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726679685; x=1727284485; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+Yad8rwljItd1lBOHF5l5s1r+xJNloMy2zxgaSK2408=; b=mwXe+WW5JYnAGvZQMv2AnPbcoC41OX5FEkhNNz6RPIx1Qn25xEH6PQ1AMMPo7up9/r onGULGh9BHA+7JdU/4U3oqgIV1qvXhoFWuWNrE5P5TtZWEIclPkrErZe54RbMdtsEH2z Sv5oO1xzJ4Tlm7QiviBSON29Hgkx9v0D5wCsnLDq6rg8Q4BdiwcARodnSs+2/EH6+R96 VbJHsB9vwDfhOgBL93Pg7F0NzeQ5QY/0rGrvfOCD/4TPcyeepnJ6kpfF5hsMky42BKYD 6BIJzo/xIIFd7Hu+EAlouSTVkJqKk76JNPujlZhSs4H/c0Xmz5EENo8Ag6tOIK/rxFH7 l23w== X-Gm-Message-State: AOJu0YzpmEE5RslQeTScYKe8hOW8rHqh0wqLfWd72h8GgCKKJDHgvvR4 rcM4Wqv4O5rWaavZvRO9CyabAal6Qsvjtvg4Molr/r+j/k9gIiu1xHobp3kjZPuqww36/eEmeUD +oRy9hC9bSs50CJTaCcwqIGMyNGxzKcGRoXde+uQuoqpp/nHS17W74i95rkmVFvfH/kbVgwRlkV jR6lrJEhMs7YfP/asYKRFJDUF6POQtc1qDhzr6aQ== X-Google-Smtp-Source: AGHT+IHl/cq+jQ767dFrl98tnvZkUQ/QQHF12lnR5PjK9WvWtCvhlaP10/fDNWK6ANt8Iq4QJQPHRw== X-Received: by 2002:a17:90b:110f:b0:2c3:40b7:1f6d with SMTP id 98e67ed59e1d1-2db9fe8d7b7mr29095182a91.0.1726679684525; Wed, 18 Sep 2024 10:14:44 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , richard.henderson@linaro.org, negge@google.com, Max Chou Subject: [PATCH v6 4/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store Date: Thu, 19 Sep 2024 01:14:09 +0800 Message-Id: <20240918171412.150107-5-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240918171412.150107-1-max.chou@sifive.com> References: <20240918171412.150107-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=max.chou@sifive.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1726679803851116600 Content-Type: text/plain; charset="utf-8" The vector unit-stride whole register load/store instructions are similar to unmasked unit-stride load/store instructions that is suitable to be optimized by using a direct access to host ram fast path. Because the vector whole register load/store instructions do not need to handle the tail agnostic, so remove the vstart early exit checking. Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/vector_helper.c | 129 +++++++++++++++++++---------------- 1 file changed, 70 insertions(+), 59 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c2fcf8b3a00..824e6401736 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -665,80 +665,91 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d_tlb) */ static void vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t = desc, - vext_ldst_elem_fn_tlb *ldst_elem, uint32_t log2_esz, - uintptr_t ra) + vext_ldst_elem_fn_tlb *ldst_tlb, + vext_ldst_elem_fn_host *ldst_host, uint32_t log2_esz, + uintptr_t ra, bool is_load) { - uint32_t i, k, off, pos; + target_ulong page_split, elems, addr; uint32_t nf =3D vext_nf(desc); uint32_t vlenb =3D riscv_cpu_cfg(env)->vlenb; uint32_t max_elems =3D vlenb >> log2_esz; + uint32_t evl =3D nf * max_elems; + uint32_t esz =3D 1 << log2_esz; + int mmu_index =3D riscv_env_mmu_index(env, false); =20 - if (env->vstart >=3D ((vlenb * nf) >> log2_esz)) { - env->vstart =3D 0; - return; + /* Calculate the page range of first page */ + addr =3D base + (env->vstart << log2_esz); + page_split =3D -(addr | TARGET_PAGE_MASK); + /* Get number of elements */ + elems =3D page_split / esz; + if (unlikely(env->vstart + elems >=3D evl)) { + elems =3D evl - env->vstart; } =20 - k =3D env->vstart / max_elems; - off =3D env->vstart % max_elems; - - if (off) { - /* load/store rest of elements of current segment pointed by vstar= t */ - for (pos =3D off; pos < max_elems; pos++, env->vstart++) { - target_ulong addr =3D base + ((pos + k * max_elems) << log2_es= z); - ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd, - ra); - } - k++; + /* Load/store elements in the first page */ + if (likely(elems)) { + vext_page_ldst_us(env, vd, addr, elems, 1, max_elems, log2_esz, + is_load, mmu_index, ldst_tlb, ldst_host, ra); } =20 - /* load/store elements for rest of segments */ - for (; k < nf; k++) { - for (i =3D 0; i < max_elems; i++, env->vstart++) { - target_ulong addr =3D base + ((i + k * max_elems) << log2_esz); - ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, = ra); + /* Load/store elements in the second page */ + if (unlikely(env->vstart < evl)) { + /* Cross page element */ + if (unlikely(page_split % esz)) { + addr =3D base + (env->vstart << log2_esz); + ldst_tlb(env, adjust_addr(env, addr), env->vstart, vd, ra); + env->vstart++; } + + addr =3D base + (env->vstart << log2_esz); + /* Get number of elements of second page */ + elems =3D evl - env->vstart; + + /* Load/store elements in the second page */ + vext_page_ldst_us(env, vd, addr, elems, 1, max_elems, log2_esz, + is_load, mmu_index, ldst_tlb, ldst_host, ra); } =20 env->vstart =3D 0; } =20 -#define GEN_VEXT_LD_WHOLE(NAME, ETYPE, LOAD_FN) \ -void HELPER(NAME)(void *vd, target_ulong base, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - vext_ldst_whole(vd, base, env, desc, LOAD_FN, \ - ctzl(sizeof(ETYPE)), GETPC()); \ -} - -GEN_VEXT_LD_WHOLE(vl1re8_v, int8_t, lde_b_tlb) -GEN_VEXT_LD_WHOLE(vl1re16_v, int16_t, lde_h_tlb) -GEN_VEXT_LD_WHOLE(vl1re32_v, int32_t, lde_w_tlb) -GEN_VEXT_LD_WHOLE(vl1re64_v, int64_t, lde_d_tlb) -GEN_VEXT_LD_WHOLE(vl2re8_v, int8_t, lde_b_tlb) -GEN_VEXT_LD_WHOLE(vl2re16_v, int16_t, lde_h_tlb) -GEN_VEXT_LD_WHOLE(vl2re32_v, int32_t, lde_w_tlb) -GEN_VEXT_LD_WHOLE(vl2re64_v, int64_t, lde_d_tlb) -GEN_VEXT_LD_WHOLE(vl4re8_v, int8_t, lde_b_tlb) -GEN_VEXT_LD_WHOLE(vl4re16_v, int16_t, lde_h_tlb) -GEN_VEXT_LD_WHOLE(vl4re32_v, int32_t, lde_w_tlb) -GEN_VEXT_LD_WHOLE(vl4re64_v, int64_t, lde_d_tlb) -GEN_VEXT_LD_WHOLE(vl8re8_v, int8_t, lde_b_tlb) -GEN_VEXT_LD_WHOLE(vl8re16_v, int16_t, lde_h_tlb) -GEN_VEXT_LD_WHOLE(vl8re32_v, int32_t, lde_w_tlb) -GEN_VEXT_LD_WHOLE(vl8re64_v, int64_t, lde_d_tlb) - -#define GEN_VEXT_ST_WHOLE(NAME, ETYPE, STORE_FN) \ -void HELPER(NAME)(void *vd, target_ulong base, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - vext_ldst_whole(vd, base, env, desc, STORE_FN, \ - ctzl(sizeof(ETYPE)), GETPC()); \ -} - -GEN_VEXT_ST_WHOLE(vs1r_v, int8_t, ste_b_tlb) -GEN_VEXT_ST_WHOLE(vs2r_v, int8_t, ste_b_tlb) -GEN_VEXT_ST_WHOLE(vs4r_v, int8_t, ste_b_tlb) -GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b_tlb) +#define GEN_VEXT_LD_WHOLE(NAME, ETYPE, LOAD_FN_TLB, LOAD_FN_HOST) \ +void HELPER(NAME)(void *vd, target_ulong base, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + vext_ldst_whole(vd, base, env, desc, LOAD_FN_TLB, LOAD_FN_HOST, \ + ctzl(sizeof(ETYPE)), GETPC(), true); \ +} + +GEN_VEXT_LD_WHOLE(vl1re8_v, int8_t, lde_b_tlb, lde_b_host) +GEN_VEXT_LD_WHOLE(vl1re16_v, int16_t, lde_h_tlb, lde_h_host) +GEN_VEXT_LD_WHOLE(vl1re32_v, int32_t, lde_w_tlb, lde_w_host) +GEN_VEXT_LD_WHOLE(vl1re64_v, int64_t, lde_d_tlb, lde_d_host) +GEN_VEXT_LD_WHOLE(vl2re8_v, int8_t, lde_b_tlb, lde_b_host) +GEN_VEXT_LD_WHOLE(vl2re16_v, int16_t, lde_h_tlb, lde_h_host) +GEN_VEXT_LD_WHOLE(vl2re32_v, int32_t, lde_w_tlb, lde_w_host) +GEN_VEXT_LD_WHOLE(vl2re64_v, int64_t, lde_d_tlb, lde_d_host) +GEN_VEXT_LD_WHOLE(vl4re8_v, int8_t, lde_b_tlb, lde_b_host) +GEN_VEXT_LD_WHOLE(vl4re16_v, int16_t, lde_h_tlb, lde_h_host) +GEN_VEXT_LD_WHOLE(vl4re32_v, int32_t, lde_w_tlb, lde_w_host) +GEN_VEXT_LD_WHOLE(vl4re64_v, int64_t, lde_d_tlb, lde_d_host) +GEN_VEXT_LD_WHOLE(vl8re8_v, int8_t, lde_b_tlb, lde_b_host) +GEN_VEXT_LD_WHOLE(vl8re16_v, int16_t, lde_h_tlb, lde_h_host) +GEN_VEXT_LD_WHOLE(vl8re32_v, int32_t, lde_w_tlb, lde_w_host) +GEN_VEXT_LD_WHOLE(vl8re64_v, int64_t, lde_d_tlb, lde_d_host) + +#define GEN_VEXT_ST_WHOLE(NAME, ETYPE, STORE_FN_TLB, STORE_FN_HOST) \ +void HELPER(NAME)(void *vd, target_ulong base, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + vext_ldst_whole(vd, base, env, desc, STORE_FN_TLB, STORE_FN_HOST, \ + ctzl(sizeof(ETYPE)), GETPC(), false); \ +} + +GEN_VEXT_ST_WHOLE(vs1r_v, int8_t, ste_b_tlb, ste_b_host) +GEN_VEXT_ST_WHOLE(vs2r_v, int8_t, ste_b_tlb, ste_b_host) +GEN_VEXT_ST_WHOLE(vs4r_v, int8_t, ste_b_tlb, ste_b_host) +GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b_tlb, ste_b_host) =20 /* * Vector Integer Arithmetic Instructions --=20 2.34.1 From nobody Sun Nov 24 15:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1726679810; cv=none; d=zohomail.com; s=zohoarc; b=eHvvsou0GKLe1F5tplB/e0ofl6frUFGHMmCSm0ZQaDs/xuIvXR2q4VXcJJlMJVOWrkvRcSZxAitnupM0b9bYxOd1ZY+jVt+9F+M68L9YFNeexsdWx1Ht1hCxac9si71+2lzyBqD069SGKXRheozHM00aBZxhYMdkfGDneEdOgYY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726679810; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2dd608e2318sm1914577a91.32.2024.09.18.10.14.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2024 10:14:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1726679688; x=1727284488; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4UxyC5GgURxAdr6hpB+84kRGnovowUYOR8ViU/IS7gA=; b=V9MiIywUhIwCOW3ByvstVLKqFjkn3Nc4zMWhkwk9s8BhZS3xkVjI5RZvvgPjy3e2H0 2fqJDiSw9fUPC1xkzfuSh2o4wkWhpYnlI2yptBm4YNJjpRxbnjBjzJyRxc66EFDs4Lcw Fd4DvO66NBBYW1YdwQeeY2SN6Ei00J1fJriOXzU5tZ7YbaBmDqvSp0qOKO1C7ldIpHF6 EOuJzMk3MCqTs2Kk5IelryjqZLBcVsIkfKwTzi/v6OXGlrnL9vV3Qbbc7kg/4FmHz3u0 m+uKuilOjh/Qk0xUHekDflPlpyRmvM04LyMKT0XUv07gJ9XvAKgjGy94pBrv+ki32wOp bmrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726679688; x=1727284488; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4UxyC5GgURxAdr6hpB+84kRGnovowUYOR8ViU/IS7gA=; b=XjpDkKeB16bD049atSJwnMVqfF2q5zw2Unr9vdlgqEdhbx2jwknRXWUXiVRsnrAWWG 53HPDd33AGs9SUgOmq6cM+zFfNhTN+30SGgsjevxcm3a38JuReJFDsj3IVtVs1homc/f Z0Sjv0BFi4vualGc4Qurt3lf02ipfy5pnZgbM3I9i/2sV9S4nM5GcYsoe+Eu3gKxsi4U qXYMTDrDRK4WQpEePBEKB8ekZ8QYwXICPzztMMUX41yhKM1aj66XsuWlJczIb5RLBAoi idTZ09/YcKV8ps6Sogpq2czlEspENyedNBW+ReFHTvs73LKfn5WEYsDTVgp9An/VIyAz PDwg== X-Gm-Message-State: AOJu0YxMJVBu0NWAy1vVjafOmbaoeO2wDTaoocEDxiahDczSlPaxPQg4 he5dvbYv4uum4mgez1C4fr4isp/KENGrlQ//nK+heL/oa0BwdLzN/90CQL2Ob1T17Vwg/Woblzl PpGaXRdZs5y5qWrojnXgkCrL+1gkgfaxg5TqLX9gtx4BHUMuXqL7fnHbo0WMlFiDYl/l1TT4ao1 npxjtXNcYd9Sqkg2s8fG/FBGCgfWWPemq9yhqwng== X-Google-Smtp-Source: AGHT+IHI7ntPiOdCMMKzQ979btH68h6+Jh4QvzEUE6JCbBWAiTHJBbIQTDMJrslSfzhSYHzn5nwAmw== X-Received: by 2002:a17:90b:886:b0:2cf:eaec:d74c with SMTP id 98e67ed59e1d1-2dbb9df6432mr21429460a91.16.1726679687711; Wed, 18 Sep 2024 10:14:47 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , richard.henderson@linaro.org, negge@google.com, Max Chou Subject: [PATCH v6 5/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride load-only-first load instructions Date: Thu, 19 Sep 2024 01:14:10 +0800 Message-Id: <20240918171412.150107-6-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240918171412.150107-1-max.chou@sifive.com> References: <20240918171412.150107-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=max.chou@sifive.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1726679811902116600 Content-Type: text/plain; charset="utf-8" The unmasked unit-stride fault-only-first load instructions are similar to the unmasked unit-stride load/store instructions that is suitable to be optimized by using a direct access to host ram fast path. Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/vector_helper.c | 98 ++++++++++++++++++++++++++---------- 1 file changed, 71 insertions(+), 27 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 824e6401736..59009a940ff 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -557,18 +557,18 @@ GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d= _tlb) * unit-stride fault-only-fisrt load instructions */ static inline void -vext_ldff(void *vd, void *v0, target_ulong base, - CPURISCVState *env, uint32_t desc, - vext_ldst_elem_fn_tlb *ldst_elem, - uint32_t log2_esz, uintptr_t ra) +vext_ldff(void *vd, void *v0, target_ulong base, CPURISCVState *env, + uint32_t desc, vext_ldst_elem_fn_tlb *ldst_tlb, + vext_ldst_elem_fn_host *ldst_host, uint32_t log2_esz, uintptr_t = ra) { uint32_t i, k, vl =3D 0; uint32_t nf =3D vext_nf(desc); uint32_t vm =3D vext_vm(desc); uint32_t max_elems =3D vext_max_elems(desc, log2_esz); uint32_t esz =3D 1 << log2_esz; + uint32_t msize =3D nf * esz; uint32_t vma =3D vext_vma(desc); - target_ulong addr, offset, remain; + target_ulong addr, offset, remain, page_split, elems; int mmu_index =3D riscv_env_mmu_index(env, false); =20 VSTART_CHECK_EARLY_EXIT(env); @@ -617,19 +617,63 @@ ProbeSuccess: if (vl !=3D 0) { env->vl =3D vl; } - for (i =3D env->vstart; i < env->vl; i++) { - k =3D 0; - while (k < nf) { - if (!vm && !vext_elem_mask(v0, i)) { - /* set masked-off elements to 1s */ - vext_set_elems_1s(vd, vma, (i + k * max_elems) * esz, - (i + k * max_elems + 1) * esz); - k++; - continue; + + if (env->vstart < env->vl) { + if (vm) { + /* Calculate the page range of first page */ + addr =3D base + ((env->vstart * nf) << log2_esz); + page_split =3D -(addr | TARGET_PAGE_MASK); + /* Get number of elements */ + elems =3D page_split / msize; + if (unlikely(env->vstart + elems >=3D env->vl)) { + elems =3D env->vl - env->vstart; + } + + /* Load/store elements in the first page */ + if (likely(elems)) { + vext_page_ldst_us(env, vd, addr, elems, nf, max_elems, + log2_esz, true, mmu_index, ldst_tlb, + ldst_host, ra); + } + + /* Load/store elements in the second page */ + if (unlikely(env->vstart < env->vl)) { + /* Cross page element */ + if (unlikely(page_split % msize)) { + for (k =3D 0; k < nf; k++) { + addr =3D base + ((env->vstart * nf + k) << log2_es= z); + ldst_tlb(env, adjust_addr(env, addr), + env->vstart + k * max_elems, vd, ra); + } + env->vstart++; + } + + addr =3D base + ((env->vstart * nf) << log2_esz); + /* Get number of elements of second page */ + elems =3D env->vl - env->vstart; + + /* Load/store elements in the second page */ + vext_page_ldst_us(env, vd, addr, elems, nf, max_elems, + log2_esz, true, mmu_index, ldst_tlb, + ldst_host, ra); + } + } else { + for (i =3D env->vstart; i < env->vl; i++) { + k =3D 0; + while (k < nf) { + if (!vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, (i + k * max_elems) * e= sz, + (i + k * max_elems + 1) * esz); + k++; + continue; + } + addr =3D base + ((i * nf + k) << log2_esz); + ldst_tlb(env, adjust_addr(env, addr), i + k * max_elem= s, + vd, ra); + k++; + } } - addr =3D base + ((i * nf + k) << log2_esz); - ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, = ra); - k++; } } env->vstart =3D 0; @@ -637,18 +681,18 @@ ProbeSuccess: vext_set_tail_elems_1s(env->vl, vd, desc, nf, esz, max_elems); } =20 -#define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - vext_ldff(vd, v0, base, env, desc, LOAD_FN, \ - ctzl(sizeof(ETYPE)), GETPC()); \ +#define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN_TLB, LOAD_FN_HOST) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldff(vd, v0, base, env, desc, LOAD_FN_TLB, \ + LOAD_FN_HOST, ctzl(sizeof(ETYPE)), GETPC()); \ } =20 -GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b_tlb) -GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h_tlb) -GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w_tlb) -GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d_tlb) +GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b_tlb, lde_b_host) +GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h_tlb, lde_h_host) +GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w_tlb, lde_w_host) +GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d_tlb, lde_d_host) =20 #define DO_SWAP(N, M) (M) #define DO_AND(N, M) (N & M) --=20 2.34.1 From nobody Sun Nov 24 15:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2dd608e2318sm1914577a91.32.2024.09.18.10.14.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2024 10:14:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1726679691; x=1727284491; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e21ToE/HJXzkFx4begXiNagynBpQzCVjg3pkA/vtkjA=; b=UTZsMiXteZSlapUNpGnwo9hu8bMhLKXSguavjagt8DeExLw3QnH20bhx5OC02QdsDP /hPHCPrtSaUlgH4/+H4fg1w8ja3peG7OvErxjJufn9K6k0yeut1TU3U3uKZusQVeAsdq Sdt9aOpgYdvn95Uj4wiGjT0Phih2SGawy3Fv5eYKZenkF0YCIug5d+dA1vMrdmbHq8at rYiHNXmFtbkDf+cEdhOIOoqK3HcGUC/FhTiKZ3SG1FD+3BzygOIL9Cl/3PoX2xF6J9Ty UWuBkoeXMT0EcLE/q+zSIroiqg7AAyymWeDbVQkDPHkekhhz6kOlAGRHFJ9ncuUN2lG4 gNpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726679691; x=1727284491; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e21ToE/HJXzkFx4begXiNagynBpQzCVjg3pkA/vtkjA=; b=oUdKTrvRKjfe6Jls13MuerWTLFY5Ral/TJJpa1+7qKyfXjtA5Tk2KYjtBCRJU0CPf1 m/lnsir9iOT95FIDK9ILPd/d5iYZVr2IYSQtR2PCnPdJvtTjwkF1iscBdFAbVPCVwVF7 45/ObDvYeRELa8HADC95NxBF4iFUhtTI0nJOGYJ4lxiJ1Pd9PHpzH3SlWlUmUzFozDUa TGZgNj+LlgV7QfxLo46p+hJVO+E8N8ckM2ApHCULYSytgLMi3HXgn8Ku7c3bjFN7pPnk UJxSq89hYH123mKYkAzFucQFmOXBkFBCLzSV3rhMyblGEpKI6ET19NFTeZKNvoTLqpTp M3aQ== X-Gm-Message-State: AOJu0Yy76iTddCUWb5yigiF15wjQVcqOz1pp2gtMNgtm23qPmeBEN03E HPYxGsiJKinG4HvcoE3CV4b0fwnisxmelrZg6FY0PzpYbiDLxhgJKwV1YLtMYS0OJWcjNvHU3Es VV6V+b+Waaw27IjFJkqinTySlhyQPjolYT7RC7rTJnkfLz5QPrm/9JnKEtuK1Nl78g2xHNoV/s9 rgeoj/lg0rOnIMJJe0Trc3Zylf5QPVwZPTjyKuJA== X-Google-Smtp-Source: AGHT+IHmPC7r4D1pHZ65Xf9g/juUNVNn4FjJQxuEfFiq9OavfkgPER76FjkG+u5oQuaOkqMJdhioSw== X-Received: by 2002:a17:90b:3888:b0:2d8:9dd2:b8a1 with SMTP id 98e67ed59e1d1-2db9ff91bd9mr21719444a91.9.1726679691211; Wed, 18 Sep 2024 10:14:51 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , richard.henderson@linaro.org, negge@google.com, Max Chou Subject: [PATCH v6 6/7] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions Date: Thu, 19 Sep 2024 01:14:11 +0800 Message-Id: <20240918171412.150107-7-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240918171412.150107-1-max.chou@sifive.com> References: <20240918171412.150107-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=max.chou@sifive.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1726679807900116600 Content-Type: text/plain; charset="utf-8" The vector unmasked unit-stride and whole register load/store instructions will load/store continuous memory. If the endian of both the host and guest architecture are the same, then we can group the element load/store to load/store more data at a time. Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/vector_helper.c | 77 +++++++++++++++++++++++++++++------- 1 file changed, 63 insertions(+), 14 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 59009a940ff..654d5e111f3 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -189,6 +189,45 @@ GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw) GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl) GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq) =20 +static inline QEMU_ALWAYS_INLINE void +vext_continus_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_tlb, + void *vd, uint32_t evl, target_ulong addr, + uint32_t reg_start, uintptr_t ra, uint32_t esz, + bool is_load) +{ + uint32_t i; + for (i =3D env->vstart; i < evl; env->vstart =3D ++i, addr +=3D esz) { + ldst_tlb(env, adjust_addr(env, addr), i, vd, ra); + } +} + +static inline QEMU_ALWAYS_INLINE void +vext_continus_ldst_host(CPURISCVState *env, vext_ldst_elem_fn_host *ldst_h= ost, + void *vd, uint32_t evl, uint32_t reg_start, void *= host, + uint32_t esz, bool is_load) +{ +#if HOST_BIG_ENDIAN + for (; reg_start < evl; reg_start++, host +=3D esz) { + ldst_host(vd, reg_start, host); + } +#else + if (esz =3D=3D 1) { + uint32_t byte_offset =3D reg_start * esz; + uint32_t size =3D (evl - reg_start) * esz; + + if (is_load) { + memcpy(vd + byte_offset, host, size); + } else { + memcpy(host, vd + byte_offset, size); + } + } else { + for (; reg_start < evl; reg_start++, host +=3D esz) { + ldst_host(vd, reg_start, host); + } + } +#endif +} + static void vext_set_tail_elems_1s(target_ulong vl, void *vd, uint32_t desc, uint32_t nf, uint32_t esz, uint32_t max_elems) @@ -297,24 +336,34 @@ vext_page_ldst_us(CPURISCVState *env, void *vd, targe= t_ulong addr, mmu_index, true, &host, ra); =20 if (flags =3D=3D 0) { - for (i =3D env->vstart; i < evl; ++i) { - k =3D 0; - while (k < nf) { - ldst_host(vd, i + k * max_elems, host); - host +=3D esz; - k++; + if (nf =3D=3D 1) { + vext_continus_ldst_host(env, ldst_host, vd, evl, env->vstart, = host, + esz, is_load); + } else { + for (i =3D env->vstart; i < evl; ++i) { + k =3D 0; + while (k < nf) { + ldst_host(vd, i + k * max_elems, host); + host +=3D esz; + k++; + } } } env->vstart +=3D elems; } else { - /* load bytes from guest memory */ - for (i =3D env->vstart; i < evl; env->vstart =3D ++i) { - k =3D 0; - while (k < nf) { - ldst_tlb(env, adjust_addr(env, addr), i + k * max_elems, v= d, - ra); - addr +=3D esz; - k++; + if (nf =3D=3D 1) { + vext_continus_ldst_tlb(env, ldst_tlb, vd, evl, addr, env->vsta= rt, + ra, esz, is_load); + } else { + /* load bytes from guest memory */ + for (i =3D env->vstart; i < evl; env->vstart =3D ++i) { + k =3D 0; + while (k < nf) { + ldst_tlb(env, adjust_addr(env, addr), i + k * max_elem= s, + vd, ra); + addr +=3D esz; + k++; + } } } } --=20 2.34.1 From nobody Sun Nov 24 15:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2dd608e2318sm1914577a91.32.2024.09.18.10.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2024 10:14:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1726679694; x=1727284494; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f408neNmJiHRMFNBITqjdfGcu6sd/hAmiLVrUqm2xBk=; b=ZHUYgjXDcDxRq2RdAX2ki5uX15Vgl0RZNgHH57zghRvRfUcRvze05mVuLHz2cmpi7J PvNDs9R/6xSzcvd8wbHqF8AQR2Vpq9MsAGYfeOOrIJVZrdKdo8mmU1500RklL4/ZNs4E xmc5pFn4vNrwX4pOdydljN6uo+bwWsaJgG/tyElyQJHFtCR80G/xK/Acp8ArVC048MEi FHIBQ+0DbXE6fE0IpPrVUwiDLd/pTanld+uAIl6xslaNaZJLTdjPAjLVPun/9+18s+Jk avCA+7tOWoo+XIb3l4LzTct9HDpKAWgDcQUBa5wa8VkeX4F+OJ/Fspjkd/rqPo3bMFRw FBqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726679694; x=1727284494; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f408neNmJiHRMFNBITqjdfGcu6sd/hAmiLVrUqm2xBk=; b=vRhAPw15x1XM8u4bqvcnl79gDHBB5ZnwdFn+BYUmys/5nW2viw73WZvH0pQupH4AcV s1053z7g+H4ZTOjD0OhAtIc9bAk3W8KIZkmGceZXOjbkA22yhn9ZKShECdmmoies2DlV eDwE4PRHSvKrttZl0po4zb65fghID2ubjPj+EDX51ng4WAbHQiJQtvnOQ+I+mBjtCLFk HeK/j+Sgl4g0sFrHehjM173cBx5UTE1m+zfHGDNSfq+D5tEAlGu42/Gb6JIfrjySvEve y4MWaxhYANbZuw8LOHRIlywpB58k1JzUhUGh0LXfvPNDgY810yWRwEYoqgXvp3JPMZQ9 cfZg== X-Gm-Message-State: AOJu0YxZhXR6fmYWlDVx2QT4qu6F3e07n4eb1CXrZ57jBKPLSLg3Glia I0xw81u5EAj9HlYsm+4L4Xoc6mkbLfeXlnBLHBd9VWLuKX+Kc5PClh0Ox1uDTY9mAl3b7AGD2t8 wv/Yt+rB9tK3PvAa63kDwMBTAd3/Xp5hdBsVdKtfuwfSBqjqyYaMgv0M/5lVooHVJl0g5LvyUNk 9pOfZ4AxUeH2JgmbG/VGEwqJj8Z3LMsOLMV8kqIA== X-Google-Smtp-Source: AGHT+IGE90+JXk1/9HlzshqC/Q6QpcF2o6vJM8Xbn1n6a1qvv2LOTEKJguy44zgsNP1e6DDtTd2ABg== X-Received: by 2002:a05:6a21:1646:b0:1cf:3ec5:e779 with SMTP id adf61e73a8af0-1cf75d7fc8emr32031945637.5.1726679694350; Wed, 18 Sep 2024 10:14:54 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , richard.henderson@linaro.org, negge@google.com, Max Chou Subject: [PATCH v6 7/7] target/riscv: Inline unit-stride ld/st and corresponding functions for performance Date: Thu, 19 Sep 2024 01:14:12 +0800 Message-Id: <20240918171412.150107-8-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240918171412.150107-1-max.chou@sifive.com> References: <20240918171412.150107-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=max.chou@sifive.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1726679801806116600 Content-Type: text/plain; charset="utf-8" In the vector unit-stride load/store helper functions. the vext_ldst_us & vext_ldst_whole functions corresponding most of the execution time. Inline the functions can avoid the function call overhead to improve the helper function performance. Signed-off-by: Max Chou Reviewed-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza --- target/riscv/vector_helper.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 654d5e111f3..0d5ed950486 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -152,14 +152,16 @@ typedef void vext_ldst_elem_fn_tlb(CPURISCVState *env= , abi_ptr addr, typedef void vext_ldst_elem_fn_host(void *vd, uint32_t idx, void *host); =20 #define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \ -static void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \ +static inline QEMU_ALWAYS_INLINE \ +void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \ uint32_t idx, void *vd, uintptr_t retaddr) \ { \ ETYPE *cur =3D ((ETYPE *)vd + H(idx)); \ *cur =3D cpu_##LDSUF##_data_ra(env, addr, retaddr); \ } \ \ -static void NAME##_host(void *vd, uint32_t idx, void *host) \ +static inline QEMU_ALWAYS_INLINE \ +void NAME##_host(void *vd, uint32_t idx, void *host) \ { \ ETYPE *cur =3D ((ETYPE *)vd + H(idx)); \ *cur =3D (ETYPE)LDSUF##_p(host); \ @@ -171,14 +173,16 @@ GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl) GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq) =20 #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ -static void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \ +static inline QEMU_ALWAYS_INLINE \ +void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \ uint32_t idx, void *vd, uintptr_t retaddr) \ { \ ETYPE data =3D *((ETYPE *)vd + H(idx)); \ cpu_##STSUF##_data_ra(env, addr, data, retaddr); \ } \ \ -static void NAME##_host(void *vd, uint32_t idx, void *host) \ +static inline QEMU_ALWAYS_INLINE \ +void NAME##_host(void *vd, uint32_t idx, void *host) \ { \ ETYPE data =3D *((ETYPE *)vd + H(idx)); \ STSUF##_p(host, data); \ @@ -317,7 +321,7 @@ GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d_tlb) */ =20 /* unmasked unit-stride load and store operation */ -static void +static inline QEMU_ALWAYS_INLINE void vext_page_ldst_us(CPURISCVState *env, void *vd, target_ulong addr, uint32_t elems, uint32_t nf, uint32_t max_elems, uint32_t log2_esz, bool is_load, int mmu_index, @@ -369,7 +373,7 @@ vext_page_ldst_us(CPURISCVState *env, void *vd, target_= ulong addr, } } =20 -static void +static inline QEMU_ALWAYS_INLINE void vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t des= c, vext_ldst_elem_fn_tlb *ldst_tlb, vext_ldst_elem_fn_host *ldst_host, uint32_t log2_esz, @@ -756,7 +760,7 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d_tlb, lde_d_host) /* * load and store whole register instructions */ -static void +static inline QEMU_ALWAYS_INLINE void vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t = desc, vext_ldst_elem_fn_tlb *ldst_tlb, vext_ldst_elem_fn_host *ldst_host, uint32_t log2_esz, --=20 2.34.1