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b=RHlpCcs4fFsCD2H6 Koejyx2oWskvUW2LgJZsfwsJyNtJfN3JboQbQJDbN9/nZbNqCT4cu4gBxZ7s5/20 6X2WgFgw17o3bC8//sbp9O0dSVbkeHmNRDdfbKE0EUsWP+nwo8nLfpkjYOra3RX3 7jcHkG67YWRbhE8U/ABY6PiwSDNgEBOWhf6ZSPY4fITrXBaEzi3kuEGXmVsUT7eK lXH0Y4+Y1JOd7BZCcrgaVyFy4AStGUXMFXVU7y0evUnywQUZFesH4NDcWpDQbNiD gg0cSS/HwJpAlm6GKW0G2EV8nsYba0pdpuFlWWiNgkwBMLwEm1xnovBo44gIqLIK WuZ1bg== From: Chalapathi V To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, clg@kaod.org, calebs@linux.ibm.com, chalapathi.v@ibm.com, chalapathi.v@linux.ibm.com, saif.abrar@linux.ibm.com, dantan@linux.vnet.ibm.com, milesg@linux.ibm.com, philmd@linaro.org, alistair@alistair23.me Subject: [PATCH v3 1/3] MAINTAINERS: Cover PowerPC SPI model in PowerNV section Date: Wed, 18 Sep 2024 11:50:43 -0500 Message-Id: <20240918165045.21298-2-chalapathi.v@linux.ibm.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20240918165045.21298-1-chalapathi.v@linux.ibm.com> References: <20240918165045.21298-1-chalapathi.v@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; 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helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1726678339195116600 From: "Philippe Mathieu-Daud=C3=A9" It is unfair to let the PowerNV SPI model to the SSI maintainers. Also include the PowerNV ones. Fixes: 29318db133 ("hw/ssi: Add SPI model") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Chalapathi V Reviewed-by: Nicholas Piggin --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ffacd60f40..b11c4edaf0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1541,8 +1541,10 @@ F: hw/ppc/pnv* F: hw/intc/pnv* F: hw/intc/xics_pnv.c F: hw/pci-host/pnv* +F: hw/ssi/pnv_spi.c F: include/hw/ppc/pnv* F: include/hw/pci-host/pnv* +F: hw/ssi/pnv_spi* F: pc-bios/skiboot.lid F: tests/qtest/pnv* F: tests/functional/test_ppc64_powernv.py --=20 2.39.5 From nobody Sun Nov 24 03:55:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1726678343; cv=none; d=zohomail.com; s=zohoarc; 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Wed, 18 Sep 2024 16:51:11 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3513420040; Wed, 18 Sep 2024 16:51:09 +0000 (GMT) Received: from gfwr515.rchland.ibm.com (unknown [9.10.239.103]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 18 Sep 2024 16:51:09 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=pp1; bh=WDx01dw0nqoaQ tq/72TUJght/MC05yJrs4L6rNPvGK4=; b=Uz5p9DpjqgIQ+SDZBzHuGW9JSNRzZ M3nQX6DGWc/V0JGjDlnQ4Z5Y4/3ov84JXonqyiifePSP7qGtH0IEJ2DF/BYn1d50 XrmfXADurJ2/Tv+RaT1Yy6tR3xtv+4rOktU5RDt+kRUjKGBSAS82KO3PpLDblZJC fdIDaUjFo4hAbJ76p4C6GkH4zEzydCRRoDcZ5E+ZqGEzcwFc7ZIHXoK1OXkdaf7d 435L+CZnAxqgIJPyt/CbrBAd5eJoTrWAYynZkwJx9yWjoB1gQLUG3KmHfYcHzqaG 2rB539LxP/qvSjt4J7N4EQc3okjMtePHuEl07hZpojm6SjQRaEaVA3PqQ== From: Chalapathi V To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, clg@kaod.org, calebs@linux.ibm.com, chalapathi.v@ibm.com, chalapathi.v@linux.ibm.com, saif.abrar@linux.ibm.com, dantan@linux.vnet.ibm.com, milesg@linux.ibm.com, philmd@linaro.org, alistair@alistair23.me Subject: [PATCH v3 2/3] hw/ssi/pnv_spi: Replace PnvXferBuffer with Fifo8 structure Date: Wed, 18 Sep 2024 11:50:44 -0500 Message-Id: <20240918165045.21298-3-chalapathi.v@linux.ibm.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20240918165045.21298-1-chalapathi.v@linux.ibm.com> References: <20240918165045.21298-1-chalapathi.v@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 9U3cw9a2OHDu_ydP2iiqwSZ3PTz6mtPK X-Proofpoint-ORIG-GUID: oroqavLGfvK2pLuUp7JovUiWKkCgB7rs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-18_10,2024-09-18_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 phishscore=0 impostorscore=0 spamscore=0 priorityscore=1501 suspectscore=0 adultscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=866 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409180110 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=chalapathi.v@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1726678345281116600 Content-Type: text/plain; charset="utf-8" In PnvXferBuffer dynamically allocating and freeing is a process overhead. Hence used an existing Fifo8 buffer with capacity of 16 bytes. Signed-off-by: Chalapathi V --- include/hw/ssi/pnv_spi.h | 3 + hw/ssi/pnv_spi.c | 167 +++++++++++++-------------------------- 2 files changed, 56 insertions(+), 114 deletions(-) diff --git a/include/hw/ssi/pnv_spi.h b/include/hw/ssi/pnv_spi.h index 8815f67d45..9878d9a25f 100644 --- a/include/hw/ssi/pnv_spi.h +++ b/include/hw/ssi/pnv_spi.h @@ -23,6 +23,7 @@ =20 #include "hw/ssi/ssi.h" #include "hw/sysbus.h" +#include "qemu/fifo8.h" =20 #define TYPE_PNV_SPI "pnv-spi" OBJECT_DECLARE_SIMPLE_TYPE(PnvSpi, PNV_SPI) @@ -37,6 +38,8 @@ typedef struct PnvSpi { SSIBus *ssi_bus; qemu_irq *cs_line; MemoryRegion xscom_spic_regs; + Fifo8 tx_fifo; + Fifo8 rx_fifo; /* SPI object number */ uint32_t spic_num; uint8_t transfer_len; diff --git a/hw/ssi/pnv_spi.c b/hw/ssi/pnv_spi.c index 9e7207bf7c..2fd5aa0a96 100644 --- a/hw/ssi/pnv_spi.c +++ b/hw/ssi/pnv_spi.c @@ -19,6 +19,7 @@ =20 #define PNV_SPI_OPCODE_LO_NIBBLE(x) (x & 0x0F) #define PNV_SPI_MASKED_OPCODE(x) (x & 0xF0) +#define PNV_SPI_FIFO_SIZE 16 =20 /* * Macro from include/hw/ppc/fdt.h @@ -35,38 +36,6 @@ } \ } while (0) =20 -/* PnvXferBuffer */ -typedef struct PnvXferBuffer { - - uint32_t len; - uint8_t *data; - -} PnvXferBuffer; - -/* pnv_spi_xfer_buffer_methods */ -static PnvXferBuffer *pnv_spi_xfer_buffer_new(void) -{ - PnvXferBuffer *payload =3D g_malloc0(sizeof(*payload)); - - return payload; -} - -static void pnv_spi_xfer_buffer_free(PnvXferBuffer *payload) -{ - free(payload->data); - free(payload); -} - -static uint8_t *pnv_spi_xfer_buffer_write_ptr(PnvXferBuffer *payload, - uint32_t offset, uint32_t length) -{ - if (payload->len < (offset + length)) { - payload->len =3D offset + length; - payload->data =3D g_realloc(payload->data, payload->len); - } - return &payload->data[offset]; -} - static bool does_rdr_match(PnvSpi *s) { /* @@ -107,8 +76,8 @@ static uint8_t get_from_offset(PnvSpi *s, uint8_t offset) return byte; } =20 -static uint8_t read_from_frame(PnvSpi *s, uint8_t *read_buf, uint8_t nr_by= tes, - uint8_t ecc_count, uint8_t shift_in_count) +static uint8_t read_from_frame(PnvSpi *s, uint8_t nr_bytes, uint8_t ecc_co= unt, + uint8_t shift_in_count) { uint8_t byte; int count =3D 0; @@ -118,8 +87,8 @@ static uint8_t read_from_frame(PnvSpi *s, uint8_t *read_= buf, uint8_t nr_bytes, if ((ecc_count !=3D 0) && (shift_in_count =3D=3D (PNV_SPI_REG_SIZE + ecc_count))) { shift_in_count =3D 0; - } else { - byte =3D read_buf[count]; + } else if (!fifo8_is_empty(&s->rx_fifo)) { + byte =3D fifo8_pop(&s->rx_fifo); trace_pnv_spi_shift_rx(byte, count); s->regs[SPI_RCV_DATA_REG] =3D (s->regs[SPI_RCV_DATA_REG] << 8)= | byte; } @@ -128,7 +97,7 @@ static uint8_t read_from_frame(PnvSpi *s, uint8_t *read_= buf, uint8_t nr_bytes, return shift_in_count; } =20 -static void spi_response(PnvSpi *s, int bits, PnvXferBuffer *rsp_payload) +static void spi_response(PnvSpi *s) { uint8_t ecc_count; uint8_t shift_in_count; @@ -144,13 +113,13 @@ static void spi_response(PnvSpi *s, int bits, PnvXfer= Buffer *rsp_payload) * First check that the response payload is the exact same * number of bytes as the request payload was */ - if (rsp_payload->len !=3D (s->N1_bytes + s->N2_bytes)) { + if ((&s->rx_fifo)->num !=3D (s->N1_bytes + s->N2_bytes)) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid response payload size in " "bytes, expected %d, got %d\n", - (s->N1_bytes + s->N2_bytes), rsp_payload->len); + (s->N1_bytes + s->N2_bytes), (&s->rx_fifo)->num); } else { uint8_t ecc_control; - trace_pnv_spi_rx_received(rsp_payload->len); + trace_pnv_spi_rx_received((&s->rx_fifo)->num); trace_pnv_spi_log_Ncounts(s->N1_bits, s->N1_bytes, s->N1_tx, s->N1_rx, s->N2_bits, s->N2_bytes, s->N2_tx, s->N2= _rx); /* @@ -175,14 +144,13 @@ static void spi_response(PnvSpi *s, int bits, PnvXfer= Buffer *rsp_payload) /* Handle the N1 portion of the frame first */ if (s->N1_rx !=3D 0) { trace_pnv_spi_rx_read_N1frame(); - shift_in_count =3D read_from_frame(s, &rsp_payload->data[0], - s->N1_bytes, ecc_count, shift_in_count); + shift_in_count =3D read_from_frame(s, s->N1_bytes, + ecc_count, shift_in_count); } /* Handle the N2 portion of the frame */ if (s->N2_rx !=3D 0) { trace_pnv_spi_rx_read_N2frame(); - shift_in_count =3D read_from_frame(s, - &rsp_payload->data[s->N1_bytes], s->N2_bytes, + shift_in_count =3D read_from_frame(s, s->N2_bytes, ecc_count, shift_in_count); } if ((s->N1_rx + s->N2_rx) > 0) { @@ -210,34 +178,36 @@ static void spi_response(PnvSpi *s, int bits, PnvXfer= Buffer *rsp_payload) } /* end of else */ } /* end of spi_response() */ =20 -static void transfer(PnvSpi *s, PnvXferBuffer *payload) +static void transfer(PnvSpi *s) { - uint32_t tx; - uint32_t rx; - PnvXferBuffer *rsp_payload =3D NULL; + uint32_t tx, rx, payload_len; + uint8_t rx_byte; =20 - rsp_payload =3D pnv_spi_xfer_buffer_new(); - for (int offset =3D 0; offset < payload->len; offset +=3D s->transfer_= len) { + payload_len =3D (&s->tx_fifo)->num; + for (int offset =3D 0; offset < payload_len; offset +=3D s->transfer_l= en) { tx =3D 0; for (int i =3D 0; i < s->transfer_len; i++) { - if ((offset + i) >=3D payload->len) { + if ((offset + i) >=3D payload_len) { tx <<=3D 8; - } else { - tx =3D (tx << 8) | payload->data[offset + i]; + } else if (!fifo8_is_empty(&s->tx_fifo)) { + tx =3D (tx << 8) | fifo8_pop(&s->tx_fifo); } } rx =3D ssi_transfer(s->ssi_bus, tx); for (int i =3D 0; i < s->transfer_len; i++) { - if ((offset + i) >=3D payload->len) { + if ((offset + i) >=3D payload_len) { break; } - *(pnv_spi_xfer_buffer_write_ptr(rsp_payload, rsp_payload->len,= 1)) =3D - (rx >> (8 * (s->transfer_len - 1) - i * 8)) & 0xFF; + rx_byte =3D (rx >> (8 * (s->transfer_len - 1) - i * 8)) & 0xFF; + if (!fifo8_is_full(&s->rx_fifo)) { + fifo8_push(&s->rx_fifo, rx_byte); + } } } - if (rsp_payload !=3D NULL) { - spi_response(s, s->N1_bits, rsp_payload); - } + spi_response(s); + /* Reset fifo for next frame */ + fifo8_reset(&s->tx_fifo); + fifo8_reset(&s->rx_fifo); } =20 static inline uint8_t get_seq_index(PnvSpi *s) @@ -348,19 +318,10 @@ static void calculate_N1(PnvSpi *s, uint8_t opcode) /* * Shift_N1 operation handler method */ -static bool operation_shiftn1(PnvSpi *s, uint8_t opcode, - PnvXferBuffer **payload, bool send_n1_alone) +static bool operation_shiftn1(PnvSpi *s, uint8_t opcode, bool send_n1_alon= e) { uint8_t n1_count; bool stop =3D false; - - /* - * If there isn't a current payload left over from a stopped sequence - * create a new one. - */ - if (*payload =3D=3D NULL) { - *payload =3D pnv_spi_xfer_buffer_new(); - } /* * Use a combination of N1 counters to build the N1 portion of the * transmit payload. @@ -411,9 +372,10 @@ static bool operation_shiftn1(PnvSpi *s, uint8_t opcod= e, */ uint8_t n1_byte =3D 0x00; n1_byte =3D get_from_offset(s, n1_count); - trace_pnv_spi_tx_append("n1_byte", n1_byte, n1_count); - *(pnv_spi_xfer_buffer_write_ptr(*payload, (*payload)->len,= 1)) =3D - n1_byte; + if (!fifo8_is_full(&s->tx_fifo)) { + trace_pnv_spi_tx_append("n1_byte", n1_byte, n1_count); + fifo8_push(&s->tx_fifo, n1_byte); + } } else { /* * We hit a shift_n1 opcode TX but the TDR is empty, tell = the @@ -440,10 +402,9 @@ static bool operation_shiftn1(PnvSpi *s, uint8_t opcod= e, "set for receive but RDR is full"); stop =3D true; break; - } else { + } else if (!fifo8_is_full(&s->tx_fifo)) { trace_pnv_spi_tx_append_FF("n1_byte"); - *(pnv_spi_xfer_buffer_write_ptr(*payload, (*payload)->len,= 1)) - =3D 0xff; + fifo8_push(&s->tx_fifo, 0xff); } } n1_count++; @@ -484,15 +445,13 @@ static bool operation_shiftn1(PnvSpi *s, uint8_t opco= de, */ if (send_n1_alone && !stop) { /* We have a TX and a full TDR or an RX and an empty RDR */ - trace_pnv_spi_tx_request("Shifting N1 frame", (*payload)->len); - transfer(s, *payload); + trace_pnv_spi_tx_request("Shifting N1 frame", (&s->tx_fifo)->num); + transfer(s); /* The N1 frame shift is complete so reset the N1 counters */ s->N2_bits =3D 0; s->N2_bytes =3D 0; s->N2_tx =3D 0; s->N2_rx =3D 0; - pnv_spi_xfer_buffer_free(*payload); - *payload =3D NULL; } return stop; } /* end of operation_shiftn1() */ @@ -588,19 +547,10 @@ static void calculate_N2(PnvSpi *s, uint8_t opcode) * Shift_N2 operation handler method */ =20 -static bool operation_shiftn2(PnvSpi *s, uint8_t opcode, - PnvXferBuffer **payload) +static bool operation_shiftn2(PnvSpi *s, uint8_t opcode) { uint8_t n2_count; bool stop =3D false; - - /* - * If there isn't a current payload left over from a stopped sequence - * create a new one. - */ - if (*payload =3D=3D NULL) { - *payload =3D pnv_spi_xfer_buffer_new(); - } /* * Use a combination of N2 counters to build the N2 portion of the * transmit payload. @@ -639,25 +589,26 @@ static bool operation_shiftn2(PnvSpi *s, uint8_t opco= de, /* Always append data for the N2 segment if it is set for TX */ uint8_t n2_byte =3D 0x00; n2_byte =3D get_from_offset(s, (s->N1_tx + n2_count)); - trace_pnv_spi_tx_append("n2_byte", n2_byte, (s->N1_tx + n2_cou= nt)); - *(pnv_spi_xfer_buffer_write_ptr(*payload, (*payload)->len, 1)) - =3D n2_byte; - } else { + if (!fifo8_is_full(&s->tx_fifo)) { + trace_pnv_spi_tx_append("n2_byte", n2_byte, + (s->N1_tx + n2_count)); + fifo8_push(&s->tx_fifo, n2_byte); + } + } else if (!fifo8_is_full(&s->tx_fifo)) { /* * Regardless of whether or not N2 is set for TX or RX, we need * the number of bytes in the payload to match the overall len= gth * of the operation. */ trace_pnv_spi_tx_append_FF("n2_byte"); - *(pnv_spi_xfer_buffer_write_ptr(*payload, (*payload)->len, 1)) - =3D 0xff; + fifo8_push(&s->tx_fifo, 0xff); } n2_count++; } /* end of while */ if (!stop) { /* We have a TX and a full TDR or an RX and an empty RDR */ - trace_pnv_spi_tx_request("Shifting N2 frame", (*payload)->len); - transfer(s, *payload); + trace_pnv_spi_tx_request("Shifting N2 frame", (&s->tx_fifo)->num); + transfer(s); /* * If we are doing an N2 TX and the TDR is full we need to clear t= he * TDR_full status. Do this here instead of up in the loop above s= o we @@ -680,8 +631,6 @@ static bool operation_shiftn2(PnvSpi *s, uint8_t opcode, s->N1_bytes =3D 0; s->N1_tx =3D 0; s->N1_rx =3D 0; - pnv_spi_xfer_buffer_free(*payload); - *payload =3D NULL; } return stop; } /* end of operation_shiftn2()*/ @@ -699,19 +648,6 @@ static void operation_sequencer(PnvSpi *s) uint8_t opcode =3D 0; uint8_t masked_opcode =3D 0; =20 - /* - * PnvXferBuffer for containing the payload of the SPI frame. - * This is a static because there are cases where a sequence has to st= op - * and wait for the target application to unload the RDR. If this occ= urs - * during a sequence where N1 is not sent alone and instead combined w= ith - * N2 since the N1 tx length + the N2 tx length is less than the size = of - * the TDR. - */ - static PnvXferBuffer *payload; - - if (payload =3D=3D NULL) { - payload =3D pnv_spi_xfer_buffer_new(); - } /* * Clear the sequencer FSM error bit - general_SPI_status[3] * before starting a sequence. @@ -840,7 +776,7 @@ static void operation_sequencer(PnvSpi *s) } s->status =3D SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_SHIFT_N1); - stop =3D operation_shiftn1(s, opcode, &payload, send_n1_al= one); + stop =3D operation_shiftn1(s, opcode, send_n1_alone); if (stop) { /* * The operation code says to stop, this can occur if: @@ -895,7 +831,7 @@ static void operation_sequencer(PnvSpi *s) /* Ok to do a Shift_N2 */ s->status =3D SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_SHIFT_N2); - stop =3D operation_shiftn2(s, opcode, &payload); + stop =3D operation_shiftn2(s, opcode); /* * If the operation code says to stop set the shifter stat= e to * wait and stop @@ -1208,6 +1144,9 @@ static void pnv_spi_realize(DeviceState *dev, Error *= *errp) s->cs_line =3D g_new0(qemu_irq, 1); qdev_init_gpio_out_named(DEVICE(s), s->cs_line, "cs", 1); =20 + fifo8_create(&s->tx_fifo, PNV_SPI_FIFO_SIZE); + fifo8_create(&s->rx_fifo, PNV_SPI_FIFO_SIZE); + /* spi scoms */ pnv_xscom_region_init(&s->xscom_spic_regs, OBJECT(s), &pnv_spi_xscom_o= ps, s, "xscom-spi", PNV10_XSCOM_PIB_SPIC_SIZE); --=20 2.39.5 From nobody Sun Nov 24 03:55:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1726678342; cv=none; d=zohomail.com; s=zohoarc; b=bKUJsJVsfje2AUUaRrvnWGIp9U0GRDOC311gos3YzZB3F1R97bopPMiBarYKHS4CJTjhzjIDUwNawC5vdeGwykthYkUAgIWxZWSKl0PLTnPy2nNUHznZ1fhziudQ/orpky0abdJkClpoMWh5GGRXjK8Vxt8VSjUDrFVQIqLpVbs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726678342; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 18 Sep 2024 16:51:12 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=pp1; bh=RBl27lVRQwuS7 XPzc9I+Jwjap3fEp6EqKfIFk9ZGTSA=; b=c+1/sr8atu+G+FdFB/i2/w99rqsTy 02YxtNwSPw11wZwwpdotRxc2c0+JYPhjfgmiuy89sJq5DWMWjjNGGUuBxrPSpE93 Nv9LSmJgqsheZG13GB/usu/7NKP+8h09Fpol7WoHw8siBp40ORacXj0tex3ylrgO FRE6nU3ByOrYc+YsF5CE4ypwBSrnGlOdEYzUhjeQeFcBmkil0STei7y1h3wEiNmH 5ZIOjLpdh8Z1dRLITEJK5KIF0ZSmaA4fok8ELKm9hJENNuFC78WfzKKt2vsAlVts NPg6Z//U7y+r0SSVN9BVhRCfA+qDGH4DKnUo4MrshuScQS2bb1U7NBf5A== From: Chalapathi V To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, clg@kaod.org, calebs@linux.ibm.com, chalapathi.v@ibm.com, chalapathi.v@linux.ibm.com, saif.abrar@linux.ibm.com, dantan@linux.vnet.ibm.com, milesg@linux.ibm.com, philmd@linaro.org, alistair@alistair23.me Subject: [PATCH v3 3/3] hw/ssi/pnv_spi: Use local var seq_index instead of get_seq_index(). Date: Wed, 18 Sep 2024 11:50:45 -0500 Message-Id: <20240918165045.21298-4-chalapathi.v@linux.ibm.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20240918165045.21298-1-chalapathi.v@linux.ibm.com> References: <20240918165045.21298-1-chalapathi.v@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: -VLKMdax0HoF6gw7vsT8n7pYpw6jlDFD X-Proofpoint-ORIG-GUID: LP4IToh9U-vHkHqrNnjU8cWbGIwtVe-G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-18_10,2024-09-18_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 suspectscore=0 mlxscore=0 mlxlogscore=802 bulkscore=0 impostorscore=0 phishscore=0 priorityscore=1501 spamscore=0 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409180110 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=chalapathi.v@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1726678343193116600 Content-Type: text/plain; charset="utf-8" Use a local variable seq_index instead of repeatedly caling get_seq_index() method. Signed-off-by: Chalapathi V --- hw/ssi/pnv_spi.c | 61 ++++++++++++++++++++++++------------------------ 1 file changed, 31 insertions(+), 30 deletions(-) diff --git a/hw/ssi/pnv_spi.c b/hw/ssi/pnv_spi.c index 2fd5aa0a96..962115f40f 100644 --- a/hw/ssi/pnv_spi.c +++ b/hw/ssi/pnv_spi.c @@ -210,15 +210,8 @@ static void transfer(PnvSpi *s) fifo8_reset(&s->rx_fifo); } =20 -static inline uint8_t get_seq_index(PnvSpi *s) -{ - return GETFIELD(SPI_STS_SEQ_INDEX, s->status); -} - static inline void next_sequencer_fsm(PnvSpi *s) { - uint8_t seq_index =3D get_seq_index(s); - s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->status, (seq_index + 1)); s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_INDEX_INC= REMENT); } =20 @@ -647,6 +640,7 @@ static void operation_sequencer(PnvSpi *s) bool stop =3D false; /* Flag to stop the sequencer */ uint8_t opcode =3D 0; uint8_t masked_opcode =3D 0; + uint8_t seq_index; =20 /* * Clear the sequencer FSM error bit - general_SPI_status[3] @@ -660,12 +654,13 @@ static void operation_sequencer(PnvSpi *s) if (GETFIELD(SPI_STS_SEQ_FSM, s->status) =3D=3D SEQ_STATE_IDLE) { s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->status, 0); } + seq_index =3D GETFIELD(SPI_STS_SEQ_INDEX, s->status); /* * There are only 8 possible operation IDs to iterate through though * some operations may cause more than one frame to be sequenced. */ - while (get_seq_index(s) < NUM_SEQ_OPS) { - opcode =3D s->seq_op[get_seq_index(s)]; + while (seq_index < NUM_SEQ_OPS) { + opcode =3D s->seq_op[seq_index]; /* Set sequencer state to decode */ s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_DECOD= E); /* @@ -682,7 +677,7 @@ static void operation_sequencer(PnvSpi *s) case SEQ_OP_STOP: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); /* A stop operation in any position stops the sequencer */ - trace_pnv_spi_sequencer_op("STOP", get_seq_index(s)); + trace_pnv_spi_sequencer_op("STOP", seq_index); =20 stop =3D true; s->status =3D SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_IDL= E); @@ -693,7 +688,7 @@ static void operation_sequencer(PnvSpi *s) =20 case SEQ_OP_SELECT_SLAVE: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); - trace_pnv_spi_sequencer_op("SELECT_SLAVE", get_seq_index(s)); + trace_pnv_spi_sequencer_op("SELECT_SLAVE", seq_index); /* * This device currently only supports a single responder * connection at position 0. De-selecting a responder is fine @@ -704,8 +699,7 @@ static void operation_sequencer(PnvSpi *s) if (s->responder_select =3D=3D 0) { trace_pnv_spi_shifter_done(); qemu_set_irq(s->cs_line[0], 1); - s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->status, - (get_seq_index(s) + 1)); + seq_index++; s->status =3D SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM= _DONE); } else if (s->responder_select !=3D 1) { qemu_log_mask(LOG_GUEST_ERROR, "Slave selection other than= 1 " @@ -732,13 +726,14 @@ static void operation_sequencer(PnvSpi *s) * applies once a valid responder select has occurred. */ s->shift_n1_done =3D false; + seq_index++; next_sequencer_fsm(s); } break; =20 case SEQ_OP_SHIFT_N1: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); - trace_pnv_spi_sequencer_op("SHIFT_N1", get_seq_index(s)); + trace_pnv_spi_sequencer_op("SHIFT_N1", seq_index); /* * Only allow a shift_n1 when the state is not IDLE or DONE. * In either of those two cases the sequencer is not in a prop= er @@ -770,8 +765,9 @@ static void operation_sequencer(PnvSpi *s) * transmission to the responder without requiring a refil= l of * the TDR between the two operations. */ - if (PNV_SPI_MASKED_OPCODE(s->seq_op[get_seq_index(s) + 1]) - =3D=3D SEQ_OP_SHIFT_N2) { + if ((seq_index !=3D 7) && + PNV_SPI_MASKED_OPCODE(s->seq_op[(seq_index + 1)]) =3D= =3D + SEQ_OP_SHIFT_N2) { send_n1_alone =3D false; } s->status =3D SETFIELD(SPI_STS_SHIFTER_FSM, s->status, @@ -793,8 +789,7 @@ static void operation_sequencer(PnvSpi *s) s->shift_n1_done =3D true; s->status =3D SETFIELD(SPI_STS_SHIFTER_FSM, s->sta= tus, FSM_SHIFT_N2); - s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->statu= s, - (get_seq_index(s) + 1)); + seq_index++; } else { /* * This is case (1) or (2) so the sequencer needs = to @@ -806,6 +801,7 @@ static void operation_sequencer(PnvSpi *s) } else { /* Ok to move on to the next index */ s->shift_n1_done =3D true; + seq_index++; next_sequencer_fsm(s); } } @@ -813,7 +809,7 @@ static void operation_sequencer(PnvSpi *s) =20 case SEQ_OP_SHIFT_N2: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); - trace_pnv_spi_sequencer_op("SHIFT_N2", get_seq_index(s)); + trace_pnv_spi_sequencer_op("SHIFT_N2", seq_index); if (!s->shift_n1_done) { qemu_log_mask(LOG_GUEST_ERROR, "Shift_N2 is not allowed if= a " "Shift_N1 is not done, shifter state =3D 0x%= llx", @@ -841,6 +837,7 @@ static void operation_sequencer(PnvSpi *s) FSM_WAIT); } else { /* Ok to move on to the next index */ + seq_index++; next_sequencer_fsm(s); } } @@ -848,7 +845,7 @@ static void operation_sequencer(PnvSpi *s) =20 case SEQ_OP_BRANCH_IFNEQ_RDR: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); - trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_RDR", get_seq_index(s= )); + trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_RDR", seq_index); /* * The memory mapping register RDR match value is compared aga= inst * the 16 rightmost bytes of the RDR (potentially with masking= ). @@ -864,6 +861,7 @@ static void operation_sequencer(PnvSpi *s) if (rdr_matched) { trace_pnv_spi_RDR_match("success"); /* A match occurred, increment the sequencer index. */ + seq_index++; next_sequencer_fsm(s); } else { trace_pnv_spi_RDR_match("failed"); @@ -871,8 +869,7 @@ static void operation_sequencer(PnvSpi *s) * Branch the sequencer to the index coded into the op * code. */ - s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->status, - PNV_SPI_OPCODE_LO_NIBBLE(opcode)); + seq_index =3D PNV_SPI_OPCODE_LO_NIBBLE(opcode); } /* * Regardless of where the branch ended up we want the @@ -891,12 +888,13 @@ static void operation_sequencer(PnvSpi *s) case SEQ_OP_TRANSFER_TDR: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); qemu_log_mask(LOG_GUEST_ERROR, "Transfer TDR is not supported\= n"); + seq_index++; next_sequencer_fsm(s); break; =20 case SEQ_OP_BRANCH_IFNEQ_INC_1: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); - trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_INC_1", get_seq_index= (s)); + trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_INC_1", seq_index); /* * The spec says the loop should execute count compare + 1 tim= es. * However we learned from engineering that we really only loop @@ -910,18 +908,18 @@ static void operation_sequencer(PnvSpi *s) * mask off all but the first three bits so we don't try to * access beyond the sequencer_operation_reg boundary. */ - s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->status, - PNV_SPI_OPCODE_LO_NIBBLE(opcode)); + seq_index =3D PNV_SPI_OPCODE_LO_NIBBLE(opcode); s->loop_counter_1++; } else { /* Continue to next index if loop counter is reached */ + seq_index++; next_sequencer_fsm(s); } break; =20 case SEQ_OP_BRANCH_IFNEQ_INC_2: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); - trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_INC_2", get_seq_index= (s)); + trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_INC_2", seq_index); uint8_t condition2 =3D GETFIELD(SPI_CTR_CFG_CMP2, s->regs[SPI_CTR_CFG_REG]); /* @@ -936,11 +934,11 @@ static void operation_sequencer(PnvSpi *s) * mask off all but the first three bits so we don't try to * access beyond the sequencer_operation_reg boundary. */ - s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, - s->status, PNV_SPI_OPCODE_LO_NIBBLE(opcode= )); + seq_index =3D PNV_SPI_OPCODE_LO_NIBBLE(opcode); s->loop_counter_2++; } else { /* Continue to next index if loop counter is reached */ + seq_index++; next_sequencer_fsm(s); } break; @@ -948,6 +946,7 @@ static void operation_sequencer(PnvSpi *s) default: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); /* Ignore unsupported operations. */ + seq_index++; next_sequencer_fsm(s); break; } /* end of switch */ @@ -956,10 +955,10 @@ static void operation_sequencer(PnvSpi *s) * we need to go ahead and end things as if there was a STOP at the * end. */ - if (get_seq_index(s) =3D=3D NUM_SEQ_OPS) { + if (seq_index =3D=3D NUM_SEQ_OPS) { /* All 8 opcodes completed, sequencer idling */ s->status =3D SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_IDL= E); - s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->status, 0); + seq_index =3D 0; s->loop_counter_1 =3D 0; s->loop_counter_2 =3D 0; s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_I= DLE); @@ -970,6 +969,8 @@ static void operation_sequencer(PnvSpi *s) break; } } /* end of while */ + /* Update sequencer index field in status.*/ + s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->status, seq_index); return; } /* end of operation_sequencer() */ =20 --=20 2.39.5