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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1726513141; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xN0e/uLlFIwe3i9VwsIxWIydNemCNI/Y0Q+7rUab0nA=; b=ZyirbdmCp9bcnnKpkYbTvTreueORelC64bDL2zX12HkLfqFPsYAhD0YEjaffEZCbBu79iy N72VhLhkR4185zdzeYkPeutH2URb5wcxsxgtaov/xjRJrER5FIeLhCL8Rw/4qKe+BByVls tOAy1dR/YkxQ/NgHfJMSZU2j5kK7k/4= X-MC-Unique: 3OF4omL6PLekXEzHU-wysA-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 08/12] hw/i2c/aspeed: Add support for 64 bit addresses Date: Mon, 16 Sep 2024 20:57:04 +0200 Message-ID: <20240916185708.574546-9-clg@redhat.com> In-Reply-To: <20240916185708.574546-1-clg@redhat.com> References: <20240916185708.574546-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1726513205806116600 From: Jamin Lin ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) and the base address of dram is "0x4 00000000" which is 64bits address. The AST2700 support the maximum DRAM size is 8 GB. The DRAM physical address range is from "0x4_0000_0000" to "0x5_FFFF_FFFF". The DRAM offset range is from "0x0_0000_0000" to "0x1_FFFF_FFFF" and it is enough to use bits [33:0] saving the dram offset. Therefore, save the high part physical address bit[1:0] of Tx/Rx buffer address as dma_dram_offset bit[33:32]. It does not need to decrease the dram physical high part address for DMA operation. (high part physical address bit[7:0] =E2=80=93 4) Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/i2c/aspeed_i2c.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 74aa5e0a160b..3ae22cb052d8 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -743,6 +743,14 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus= , hwaddr offset, __func__); break; =20 + /* + * The AST2700 support the maximum DRAM size is 8 GB. + * The DRAM offset range is from 0x0_0000_0000 to + * 0x1_FFFF_FFFF and it is enough to use bits [33:0] + * saving the dram offset. + * Therefore, save the high part physical address bit[1:0] + * of Tx/Rx buffer address as dma_dram_offset bit[33:32]. + */ case A_I2CM_DMA_TX_ADDR_HI: if (!aic->has_dma64) { qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n", @@ -752,6 +760,8 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus,= hwaddr offset, bus->regs[R_I2CM_DMA_TX_ADDR_HI] =3D FIELD_EX32(value, I2CM_DMA_TX_ADDR_HI, ADDR_HI); + bus->dma_dram_offset =3D deposit64(bus->dma_dram_offset, 32, 32, + extract32(value, 0, 2)); break; case A_I2CM_DMA_RX_ADDR_HI: if (!aic->has_dma64) { @@ -762,6 +772,8 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus,= hwaddr offset, bus->regs[R_I2CM_DMA_RX_ADDR_HI] =3D FIELD_EX32(value, I2CM_DMA_RX_ADDR_HI, ADDR_HI); + bus->dma_dram_offset =3D deposit64(bus->dma_dram_offset, 32, 32, + extract32(value, 0, 2)); break; case A_I2CS_DMA_TX_ADDR_HI: qemu_log_mask(LOG_UNIMP, @@ -777,6 +789,8 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus,= hwaddr offset, bus->regs[R_I2CS_DMA_RX_ADDR_HI] =3D FIELD_EX32(value, I2CS_DMA_RX_ADDR_HI, ADDR_HI); + bus->dma_dram_offset =3D deposit64(bus->dma_dram_offset, 32, 32, + extract32(value, 0, 2)); break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\= n", --=20 2.46.0