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[27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.51.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:51:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726501906; x=1727106706; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q8SeRNxqA0kdGYXuMPPKRU3j4MVX/4+712bEYl1oABA=; b=e7fps7NagOTBehf4dmz4emnrSS72LqJ320yvMm3wxDVZpTJ99ZF9ZX0hOcVtNZZ+1S +XXyILR7i4oMr4ju/Hf2xi52sTY79Z/lCO9ATCr2aRJNK94esEd9NLdmWsVUUMoUouLC J1hnpYTMz+bmUhoDIBkfQagOdPa3L08ImdtGcQWnxXFo+rD8iH+pJEN9xi/EI/cEF71L bDgPHGYuHeaeiXJNVNvdom+VFImQSC/ozfL3mEsyjvptSpn0vOdbVy+mGO7SAEsMRbHR JuJ/hrO/8DKCjH9GiXxzlXhKl8268QZt3HU7ZpHoc8ndi35RSVwEXQ/eeXnsq4ckgPM4 d4mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726501906; x=1727106706; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q8SeRNxqA0kdGYXuMPPKRU3j4MVX/4+712bEYl1oABA=; b=t3IIHUg7fe9tLOeq+5SL+J7gS5CkwGHDOo2vb3C/mtsCNVMwd2e9OvY8igcCjk8Azg 9UDnuLAYQ4TP6JYHbMmZqBy3Eu30Kj2gRWyfwib/jt5UgZNocz/KeZSZaNneNqbfDdIs y0fnAH6Aj4fegmD4UjaW2rU1rpOPyFF1EHS+wQ/9KN9xCar+o/dVO+l2+8TykFspugJ2 fzY8ExqmUbnuyrOVVp2oRGOdS5Dv9cD0mSjrXk12a0PQA0EyysQS8sPypgGzGK4i5Yt6 qno2aAdg6JN1A+SOsBdDB2zkVNUHumRFsf9Ny/b6axmgjvIUBfuJJm87IW4LKp+BvuDq Caww== X-Forwarded-Encrypted: i=1; AJvYcCW0Uok1crTMoM/O8IxCizxsFROuV+Uxj0lttXppQ5Neim1pG3RQhHj7hxR9HSTvBlETgyxFc1j6cb5i@nongnu.org X-Gm-Message-State: AOJu0YwjtdxzmHiMbplmgB9H9Zi/IkZxUAIqAHIIA18sQv8sIZlTLtQR n7RkFNgKZ6t0v5kMyOlBArz2PXRVL8xT7g4XDaDth1zc8iRcjoWqdTbzE5dl X-Google-Smtp-Source: AGHT+IFE9rMRERxsAPLM58glQqDq7TEDtku+nN95/z+RWA38CMx/Sbe8XXQXl/ae8LoXEdkY248COw== X-Received: by 2002:a17:903:1c5:b0:206:9ab3:2ec1 with SMTP id d9443c01a7336-2078295da1fmr141000975ad.22.1726501906204; Mon, 16 Sep 2024 08:51:46 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Richard Henderson Subject: [PATCH v7 04/17] bsd-user: Implement RISC-V TLS register setup Date: Tue, 17 Sep 2024 01:51:06 +1000 Message-Id: <20240916155119.14610-5-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1726501992719116600 Content-Type: text/plain; charset="utf-8" From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch.h | 27 +++++++++++++++++++++++++++ bsd-user/riscv/target_arch_cpu.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 bsd-user/riscv/target_arch.h create mode 100644 bsd-user/riscv/target_arch_cpu.c diff --git a/bsd-user/riscv/target_arch.h b/bsd-user/riscv/target_arch.h new file mode 100644 index 0000000000..26ce07f343 --- /dev/null +++ b/bsd-user/riscv/target_arch.h @@ -0,0 +1,27 @@ +/* + * RISC-V specific prototypes + * + * Copyright (c) 2019 Mark Corbin + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARCH_H +#define TARGET_ARCH_H + +#include "qemu.h" + +void target_cpu_set_tls(CPURISCVState *env, target_ulong newtls); + +#endif /* TARGET_ARCH_H */ diff --git a/bsd-user/riscv/target_arch_cpu.c b/bsd-user/riscv/target_arch_= cpu.c new file mode 100644 index 0000000000..44e25d2ddf --- /dev/null +++ b/bsd-user/riscv/target_arch_cpu.c @@ -0,0 +1,29 @@ +/* + * RISC-V CPU related code + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ +#include "qemu/osdep.h" + +#include "target_arch.h" + +#define TP_OFFSET 16 + +/* Compare with cpu_set_user_tls() in riscv/riscv/vm_machdep.c */ +void target_cpu_set_tls(CPURISCVState *env, target_ulong newtls) +{ + env->gpr[xTP] =3D newtls + TP_OFFSET; +} --=20 2.34.1