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helo=lists.gnu.org; Received-SPF: pass client-ip=103.168.172.155; envelope-from=jiaxun.yang@flygoat.com; helo=fhigh4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @flygoat.com) X-ZM-MESSAGEID: 1726315855849116600 Use stl_p to write instructions so that host endian conversion will be performed. Replace mailbox read/write on LoongArch32 systems with 32bit IOCSR instructions to prevent illegal instructions. Signed-off-by: Jiaxun Yang --- hw/loongarch/boot.c | 107 +++++++++++++++++++++++++++++-------------------= ---- 1 file changed, 59 insertions(+), 48 deletions(-) diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c index 4d01c01594e2..5a1cc5b79b41 100644 --- a/hw/loongarch/boot.c +++ b/hw/loongarch/boot.c @@ -22,53 +22,64 @@ unsigned memmap_entries; ram_addr_t initrd_offset; uint64_t initrd_size; =20 -static const unsigned int slave_boot_code[] =3D { - /* Configure reset ebase. */ - 0x0400302c, /* csrwr $t0, LOONGARCH_CSR_EENTRY */ - - /* Disable interrupt. */ - 0x0380100c, /* ori $t0, $zero,0x4 */ - 0x04000180, /* csrxchg $zero, $t0, LOONGARCH_CSR_CRMD */ - - /* Clear mailbox. */ - 0x1400002d, /* lu12i.w $t1, 1(0x1) */ - 0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */ - 0x06481da0, /* iocsrwr.d $zero, $t1 */ - - /* Enable IPI interrupt. */ - 0x1400002c, /* lu12i.w $t0, 1(0x1) */ - 0x0400118c, /* csrxchg $t0, $t0, LOONGARCH_CSR_ECFG */ - 0x02fffc0c, /* addi.d $t0, $r0,-1(0xfff) */ - 0x1400002d, /* lu12i.w $t1, 1(0x1) */ - 0x038011ad, /* ori $t1, $t1, CORE_EN_OFF */ - 0x064819ac, /* iocsrwr.w $t0, $t1 */ - 0x1400002d, /* lu12i.w $t1, 1(0x1) */ - 0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */ - - /* Wait for wakeup <.L11>: */ - 0x06488000, /* idle 0x0 */ - 0x03400000, /* andi $zero, $zero, 0x0 */ - 0x064809ac, /* iocsrrd.w $t0, $t1 */ - 0x43fff59f, /* beqz $t0, -12(0x7ffff4) # 48 <.L11> */ - - /* Read and clear IPI interrupt. */ - 0x1400002d, /* lu12i.w $t1, 1(0x1) */ - 0x064809ac, /* iocsrrd.w $t0, $t1 */ - 0x1400002d, /* lu12i.w $t1, 1(0x1) */ - 0x038031ad, /* ori $t1, $t1, CORE_CLEAR_OFF */ - 0x064819ac, /* iocsrwr.w $t0, $t1 */ - - /* Disable IPI interrupt. */ - 0x1400002c, /* lu12i.w $t0, 1(0x1) */ - 0x04001180, /* csrxchg $zero, $t0, LOONGARCH_CSR_ECFG */ - - /* Read mail buf and jump to specified entry */ - 0x1400002d, /* lu12i.w $t1, 1(0x1) */ - 0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */ - 0x06480dac, /* iocsrrd.d $t0, $t1 */ - 0x00150181, /* move $ra, $t0 */ - 0x4c000020, /* jirl $zero, $ra,0 */ -}; +static void generate_secondary_boot_code(void *boot_code, bool is_64bit) +{ + uint32_t *p =3D boot_code; + + /* Configure reset ebase. */ + stl_p(p++, 0x0400302c); /* csrwr $t0, LOONGARCH_CSR_EENTRY */ + + /* Disable interrupt. */ + stl_p(p++, 0x0380100c); /* ori $t0, $zero,0x4 */ + stl_p(p++, 0x04000180); /* csrxchg $zero, $t0, LOONGARCH_CSR_CRMD */ + + /* Clear mailbox. */ + stl_p(p++, 0x1400002d); /* lu12i.w $t1, 1(0x1) */ + stl_p(p++, 0x038081ad); /* ori $t1, $t1, CORE_BUF_20 */ + if (is_64bit) { + stl_p(p++, 0x06481da0); /* iocsrwr.d $zero, $t1 */ + } else { + stl_p(p++, 0x064819a0); /* iocsrwr.w $zero, $t1 */ + } + + /* Enable IPI interrupt. */ + stl_p(p++, 0x1400002c); /* lu12i.w $t0, 1(0x1) */ + stl_p(p++, 0x0400118c); /* csrxchg $t0, $t0, LOONGARCH_CSR_ECFG */ + stl_p(p++, 0x02fffc0c); /* addi.d $t0, $r0, -1(0xfff) */ + stl_p(p++, 0x1400002d); /* lu12i.w $t1, 1(0x1) */ + stl_p(p++, 0x038011ad); /* ori $t1, $t1, CORE_EN_OFF */ + stl_p(p++, 0x064819ac); /* iocsrwr.w $t0, $t1 */ + stl_p(p++, 0x1400002d); /* lu12i.w $t1, 1(0x1) */ + stl_p(p++, 0x038081ad); /* ori $t1, $t1, CORE_BUF_20 */ + + /* Wait for wakeup <.L11>: */ + stl_p(p++, 0x06488000); /* idle 0x0 */ + stl_p(p++, 0x03400000); /* andi $zero, $zero, 0x0 */ + stl_p(p++, 0x064809ac); /* iocsrrd.w $t0, $t1 */ + stl_p(p++, 0x43fff59f); /* beqz $t0, -12(0x7ffff4) # 48 <.L11> */ + + /* Read and clear IPI interrupt. */ + stl_p(p++, 0x1400002d); /* lu12i.w $t1, 1(0x1) */ + stl_p(p++, 0x064809ac); /* iocsrrd.w $t0, $t1 */ + stl_p(p++, 0x1400002d); /* lu12i.w $t1, 1(0x1) */ + stl_p(p++, 0x038031ad); /* ori $t1, $t1, CORE_CLEAR_OFF */ + stl_p(p++, 0x064819ac); /* iocsrwr.w $t0, $t1 */ + + /* Disable IPI interrupt. */ + stl_p(p++, 0x1400002c); /* lu12i.w $t0, 1(0x1) */ + stl_p(p++, 0x04001180); /* csrxchg $zero, $t0, LOONGARCH_CSR_ECFG */ + + /* Read mail buf and jump to specified entry. */ + stl_p(p++, 0x1400002d); /* lu12i.w $t1, 1(0x1) */ + stl_p(p++, 0x038081ad); /* ori $t1, $t1, CORE_BUF_20 */ + if (is_64bit) { + stl_p(p++, 0x06480dac); /* iocsrrd.d $t0, $t1 */ + } else { + stl_p(p++, 0x064809ac); /* iocsrrd.w $t0, $t1 */ + } + stl_p(p++, 0x00150181); /* move $ra, $t0 */ + stl_p(p++, 0x4c000020); /* jirl $zero, $ra, 0 */ +} =20 static inline void *guidcpy(void *dst, const void *src) { @@ -379,7 +390,7 @@ static void loongarch_direct_kernel_boot(struct loongar= ch_boot_info *info) =20 /* Load slave boot code at pflash0 . */ void *boot_code =3D g_malloc0(VIRT_FLASH0_SIZE); - memcpy(boot_code, &slave_boot_code, sizeof(slave_boot_code)); + generate_secondary_boot_code(boot_code, is_la64(&lacpu->env)); rom_add_blob_fixed("boot_code", boot_code, VIRT_FLASH0_SIZE, VIRT_FLAS= H0_BASE); =20 CPU_FOREACH(cs) { --=20 2.46.0